Patents by Inventor Tatung Chow

Tatung Chow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230044490
    Abstract: A method of determining a mask pattern for a target pattern to be printed on a substrate. The method includes partitioning a portion of a design layout including the target pattern into a plurality of cells with reference to a given location on the target pattern; assigning a plurality of variables within a particular cell of the plurality of cells, the particular cell including the target pattern or a portion thereof; and determining, based on values of the plurality of variables, the mask pattern for the target pattern such that a performance metric of a patterning process utilizing the mask pattern is within a desired performance range.
    Type: Application
    Filed: November 21, 2020
    Publication date: February 9, 2023
    Inventors: Quan ZHANG, Tatung CHOW, Been-Der CHEN, Yen-Wen LU
  • Patent number: 8473878
    Abstract: During a calculation technique, at least a portion of a target pattern associated with an integrated-circuit design is modified so that polygons in the target pattern, which represent features in the design, result in acceptable accuracy during a photolithographic process that fabricates the target pattern on a semiconductor die. In particular, a set of polygon parameters associated with the polygons are modified, as needed, so that a cost function that corresponds to a difference between a modified target pattern and an estimated target pattern produced during the photolithographic process meets a termination criterion. A mask pattern that can fabricate the modified target pattern on the semiconductor die is calculated using an inverse optical calculation in which the modified target pattern is at an image plane of an optical path associated with the photolithographic process and the mask pattern is at an object plane of the optical path.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: June 25, 2013
    Assignee: Synopsys, Inc.
    Inventors: Tatung Chow, Changqing Hu, Donghwan Son, David H. Kim, Thomas C. Cecil
  • Publication number: 20130139116
    Abstract: During a calculation technique, at least a portion of a target pattern associated with an integrated-circuit design is modified so that polygons in the target pattern, which represent features in the design, result in acceptable accuracy during a photolithographic process that fabricates the target pattern on a semiconductor die. In particular, a set of polygon parameters associated with the polygons are modified, as needed, so that a cost function that corresponds to a difference between a modified target pattern and an estimated target pattern produced during the photolithographic process meets a termination criterion. A mask pattern that can fabricate the modified target pattern on the semiconductor die is calculated using an inverse optical calculation in which the modified target pattern is at an image plane of an optical path associated with the photolithographic process and the mask pattern is at an object plane of the optical path.
    Type: Application
    Filed: November 28, 2011
    Publication date: May 30, 2013
    Applicant: Luminescent Technologies, Inc.
    Inventors: Tatung Chow, Changqing Hu, Donghwan Son, David H. Kim, Thomas C. Cecil
  • Patent number: 8279409
    Abstract: The present invention provides a method for calibrating a computational model of a lithography process by calculating a demerit function using an intensity measurement at a location of a wafer; and calibrating the lithography model or a mask making model by determining values of parameters of the computational model using the calculated demerit function. The method may also use a second demerit function that is defined by the sum of squares of differences between a simulated and measured critical dimensions of a feature on the wafer.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: October 2, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Abdurrahman Sezginer, Hsu-Ting Huang, Jesus Orsely Carrero, Tatung Chow, Kostyantyn Chuyeshov, Gokhan Percin