Patents by Inventor Te-Hsin Lin
Te-Hsin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240170551Abstract: A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, a dielectric structure, and a spacer. The control gate and the select gate are over a channel region of the semiconductor substrate and separated from each other. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part. The select gate is between the spacer and the control gate, and the select gate is separated from the spacer by the second part of the dielectric structure.Type: ApplicationFiled: February 1, 2024Publication date: May 23, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Han LIN, Wei-Cheng WU, Te-Hsin CHIU
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Publication number: 20240145475Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor is of a first type in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is of a second type arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device further includes a first conductive line in a third layer between the first and second layers. The first conductive line electrically connects a first source/drain region of the first active region to a second source/drain region of the second active region. The gate comprises an intermediate portion disposed between the first active region and the second active region, wherein the first conductive line crosses the gate at the intermediate portion.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Inventors: SHIH-WEI PENG, TE-HSIN CHIU, WEI-CHENG LIN, JIANN-TYNG TZENG
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Patent number: 11950413Abstract: An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-? dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-?) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one ?m2. Polysilicon gates with these adaptations may be operative with gate voltages of 10 V or higher and may be used in embedded memory devices.Type: GrantFiled: December 13, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Te-Hsin Chiu
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Publication number: 20240105601Abstract: An integrated circuit includes a plurality of first layer deep lines, a plurality of first layer shallow lines, a plurality of second layer deep lines, and a plurality of second layer shallow lines. The integrated circuit also includes a first active device and a second active device coupled between a conducting path that has a low resistivity portion and a low capacitivity portion. The first active device has an output coupled to a first layer deep line that is in the low resistivity portion. The second active device has an input coupled to a first layer shallow line that is in the low capacitivity portion. The low resistivity portion excludes the first layer shallow lines and the second layer shallow lines, and the low capacitivity portion excludes the first layer deep lines and the second layer deep lines.Type: ApplicationFiled: November 28, 2023Publication date: March 28, 2024Inventors: Wei-An LAI, Te-Hsin CHIU, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG, Chia-Tien WU
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Patent number: 11943921Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. Each memory cell structure of the plurality of memory cell structures comprises a control gate electrode disposed over the substrate, a select gate electrode disposed on one side of the control gate electrode, and a spacer between the control gate electrode and the select gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with a sidewall surface of the select gate electrode within the memory region. A lower inter-layer dielectric layer is disposed on the CESL between the plurality of memory cell structures within the memory region.Type: GrantFiled: July 27, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Te-Hsin Chiu, Wei Cheng Wu
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Patent number: 11935830Abstract: An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.Type: GrantFiled: August 31, 2021Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Hsin Chiu, Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng, Jiun-Wei Lu
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Patent number: 11923427Abstract: A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, and a dielectric structure. The semiconductor substrate has a drain region, a source region, and a channel region between the drain region and the source region. The control gate is over the channel region of the semiconductor substrate. The select gate is over the channel region of the semiconductor substrate and separated from the control gate. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part.Type: GrantFiled: February 25, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Han Lin, Wei-Cheng Wu, Te-Hsin Chiu
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Patent number: 11923369Abstract: An integrated circuit includes a set of power rails on a back-side of a substrate, a first flip-flop, a second flip-flop and a third flip-flop. The set of power rails extend in a first direction. The first flip-flop includes a first set of conductive structures extending in the first direction. The second flip-flop abuts the first flip-flop at a first boundary, and includes a second set of conductive structures extending in the first direction. The third flip-flop abuts the second flip-flop at a second boundary, and includes a third set of conductive structures extending in the first direction. The first, second and third flip-flop are on a first metal layer and are on a front-side of the substrate opposite from the back-side. The second set of conductive structures are offset from the first boundary and the second boundary in a second direction.Type: GrantFiled: February 25, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Hsin Chiu, Wei-Cheng Lin, Wei-An Lai, Jiann-Tyng Tzeng
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Patent number: 11916070Abstract: Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.Type: GrantFiled: June 11, 2021Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Hsin Chiu, Kam-Tou Sio, Shang-Wei Fang, Wei-Cheng Lin, Jiann-Tyng Tzeng
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Publication number: 20180329742Abstract: Frame running time of a device is estimated dynamically. The device includes a processor that executes threads of an application, and a graphics processor that receives commands from the processor for rendering frames. For each frame, the processor records a timer period for each thread in a set of threads that contribute to operations of a render thread. The render thread writes the commands for the graphics processor to render the frames. Each thread in the set of threads has a corresponding timer that controls a sleep state of the thread. The processor calculates a frame non-running time for a current frame using recorded one or more timer periods, and calculates the frame running time for the current frame by subtracting the frame non-running time from an end-to-end frame period.Type: ApplicationFiled: May 8, 2018Publication date: November 15, 2018Inventors: Tzu-Jen Lo, Yu-Ming Lin, Te-Hsin Lin, Shu-Mei Huang, Po-Ting Chen