Abstract: In a method of manufacturing a semiconductor device, an n-type source/drain epitaxial layer and a p-type source/drain epitaxial layer respectively formed, a dielectric layer is formed over the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer, a first opening is formed in the dielectric layer to expose a part of the n-type source/drain epitaxial layer and a second opening is formed in the dielectric layer to expose a part of the p-type source/drain epitaxial layer, and the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer respectively recessed. A recessing amount of the n-type source/drain epitaxial layer is different from a recessing amount of the p-type source/drain epitaxial layer.

Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.

Abstract: A system and method for efficiently designing a through silicon via (TSV) macro blocks are described. In various implementations, the circuitry of a processor executes instructions of a place and route tool that provides automatic placement of macro blocks and standard cells on an integrated circuit die based on a copy of a netlist of the integrated circuit being designed and a copy of a standard cell library that includes a variety of standard cells and macro blocks. The processor places two functional macros in the floorplan with a channel between them. In the channel, the processor places a TSV macro that includes at least one boundary cell inside of the TSV macro. The processor prevents placement of a boundary cell adjacent to at least one side of the TSV macro despite empty space exists due to no standard cells or macros about the at least one side.

Abstract: An execution method of an online discussion board and a server using the same are provided. The server includes an information collection unit, an analyzing unit, a discussion board management unit and a recording unit. The information collection unit is configured to obtain a plurality of process problem messages. The analyzing unit is configured to automatically obtain a process analysis report according to the process problem messages. The discussion board management unit is configured to automatically create the online discussion board. At least two users are invited to enter the online discussion board. The process analysis report is shown in the online discussion board. The recording unit is configured to store a discussion record on the online discussion board. The online discussion board is held for a period of time.

Abstract: A training method of a semiconductor process prediction model, a semiconductor process prediction device, and a semiconductor process prediction method are provided. The training method of the semiconductor process prediction model includes the following steps. The semiconductor process was performed on several samples. A plurality of process data of the samples are obtained. A plurality of electrical measurement data of the samples are obtained. Some of the samples having physical defects are filtered out according to the process data. The semiconductor process prediction model is trained according to the process data and the electrical measurement data of the filtered samples.

Abstract: A semiconductor manufacturing process prediction method and a semiconductor manufacturing process prediction device are provided. The semiconductor manufacturing process prediction method includes the following steps. A plurality of process data are obtained. According to the process data, a machine learning model is used to execute prediction and obtain a prediction confidence and a prediction yield. Whether the prediction confidence is lower than a predetermined level is determined. If the prediction confidence is lower than the predetermined level, the machine learning model is modified. According to the process data, the prediction yield is adjusted.

Abstract: An operation method and an operation device of a failure detection and classification (FDC) model are provided. The operation method of the FDC model includes the following steps. A plurality of raw traces are continuously obtained. If the raw traces have started to be changed from the first waveform to the second waveform, whether at least N pieces in the race traces have been changed to the second waveform is determined. If at least N pieces in the raw traces have been changed to the second waveform, the raw traces which have been changed to the second waveform are automatically segmented to obtain several windows. An algorithm is automatically set for each of the windows. Through each of the algorithms, an indicator of each of the windows is obtained. The FDC model is retrained based on these indicators.

Abstract: An operation method and an operation device of a failure detection and classification (FDC) model are provided. The operation method of the FDC model includes the following steps. A plurality of raw traces are continuously obtained. If the raw traces have started to be changed from the first waveform to the second waveform, whether at least N pieces in the race traces have been changed to the second waveform is determined. If at least N pieces in the raw traces have been changed to the second waveform, the raw traces which have been changed to the second waveform are automatically segmented to obtain several windows. An algorithm is automatically set for each of the windows. Through each of the algorithms, an indicator of each of the windows is obtained. The FDC model is retrained based on these indicators.

Abstract: Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.

Abstract: Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.

Abstract: A management method for a non-volatile memory comprises the steps of providing the non-volatile memory with at least one block having a plurality of pages to store user data and parity data; dividing at least one of the pages into a plurality of partitions each including the user data and parity data; determining codeword length of each of the partitions, the codeword length comprising message length with sufficient storage to store the user data and parity length storing the parity data; and storing extra parity data in the partition with the codeword length. When storing extra parity data in the codeword length, the parity length is increased and the message length is decreased.

Abstract: A management method for a non-volatile memory comprises the steps of providing the non-volatile memory with at least one block having a plurality of pages to store user data and parity data; dividing at least one of the pages into a plurality of partitions each including the user data and parity data; determining codeword length of each of the partitions, the codeword length comprising message length with sufficient storage to store the user data and parity length storing the parity data; and storing extra parity data in the partition with the codeword length. When storing extra parity data in the codeword length, the parity length is increased and the message length is decreased.