Patents by Inventor Te Liang

Te Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11990167
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Jhih Shen, Kuang-I Liu, Joung-Wei Liou, Jinn-Kwei Liang, Yi-Wei Chiu, Chin-Hsing Lin, Li-Te Hsu, Han-Ting Tsai, Cheng-Yi Wu, Shih-Ho Lin
  • Patent number: 11960253
    Abstract: A system and a method for parameter optimization with adaptive search space and a user interface using the same are provided. The system includes a data acquisition unit, an adaptive adjustment unit and an optimization search unit. The data acquisition unit obtains a set of executed values of several operating parameters and a target parameter. The adaptive adjustment unit includes a parameter space transformer and a search range definer. The parameter space transformer performs a space transformation on a parameter space of the operating parameters according to the executed values. The search range definer defines a parameter search range in a transformed parameter space based on the sets of the executed values. The optimization search unit takes the parameter search range as a limiting condition and takes optimizing the target parameter as a target to search for a set of recommended values of the operating parameters.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: April 16, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Po-Yu Huang, Chun-Fang Chen, Hong-Chi Ku, Te-Ming Chen, Chien-Liang Lai, Sen-Chia Chang
  • Publication number: 20240090234
    Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Te-Wei Yeh, Chien-Liang Wu
  • Patent number: 11916155
    Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: February 27, 2024
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chien-Hsiu Huang, Bo-Jhih Chen, Kuo-Ming Chiu, Meng-Sung Chou, Wei-Te Cheng, Kai-Chieh Liang, Yun-Ta Chen, Yu-Han Wang
  • Patent number: 11682818
    Abstract: An antennas-in-package (AiP) verification board is provided, which includes a carrier board configured for disposing an antenna array or an electronic circuit; and a plurality of SMPM connectors. The plurality of SMPM connectors are arranged in an array on the carrier board and electrically connected with the antenna array or the electronic circuit of the carrier board for testing the characteristics of the antenna array on the carrier board or the characteristics of the electronic circuit on the carrier board. The AiP verification board is fixed on a beamforming test platform. In addition to the aforementioned AiP verification board, an AiP verification board including a plurality of adaptor structures and an AiP verification board including a plurality of connectors and a plurality of adaptor structures are also provided.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: June 20, 2023
    Assignee: TMY Technology Inc.
    Inventors: Su-Wei Chang, Chueh-Jen Lin, Wen-Tsai Tsai, Tzu-Chieh Hung, Yang Tai, Chien-Tse Fang, Po-Chia Huang, Te-Liang Sun, Ying-Yen Lu
  • Publication number: 20230136676
    Abstract: A device includes a source region, a drain region, a channel region, a pair of depletion gates, an accumulation gate, and a superconductive resonator. The channel region is between the source region and the drain region. The pair of depletion gates are spaced apart from each other. The pair of depletion gates both overlap the channel region and define a quantum dot qubit region in the channel region and between the pair of depletion gates. The accumulation gate is above and crossing the pair of depletion gates. The superconductive resonator is laterally adjacent the quantum dot qubit region.
    Type: Application
    Filed: April 7, 2022
    Publication date: May 4, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Yu-Chen YEH, Chi-Te LIANG, Hsi-Sheng GOAN
  • Publication number: 20210050674
    Abstract: An antennas-in-package (AiP) verification board is provided, which includes a carrier board configured for disposing an antenna array or an electronic circuit; and a plurality of SMPM connectors. The plurality of SMPM connectors are arranged in an array on the carrier board and electrically connected with the antenna array or the electronic circuit of the carrier board for testing the characteristics of the antenna array on the carrier board or the characteristics of the electronic circuit on the carrier board. The AiP verification board is fixed on a beamforming test platform. In addition to the aforementioned AiP verification board, an AiP verification board including a plurality of adaptor structures and an AiP verification board including a plurality of connectors and a plurality of adaptor structures are also provided.
    Type: Application
    Filed: August 14, 2020
    Publication date: February 18, 2021
    Inventors: Su-Wei Chang, Chueh-Jen Lin, Wen-Tsai Tsai, Tzu-Chieh Hung, Yang Tai, Chien-Tse Fang, Po-Chia Huang, Te-Liang Sun, Ying-Yen Lu
  • Patent number: 10381709
    Abstract: A multi-band antenna structure includes a substrate having a first wiring area located on one side surface thereof. The first wiring area has a first metal trace, a second metal trace and a connecting portion formed therein. The first and the second metal trace are respectively in an elongated spiral pattern; and the connecting portion is electrically connected at two opposite ends to the first and the second metal trace. The multi-band antenna structure can be directly integrated into electrical circuits on a circuit board to provide the advantages of reduced manufacturing cost and capable of transmitting or receiving multiple bands of signals.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: August 13, 2019
    Assignee: Keycore Technology Corp.
    Inventors: Yang-Te Liang, Po-Wei Chiu, Sheng-Ruei Hsu, Wei-Cheng Lin, Chien-Jen Hsiao, Shih-Hsiu Tseng
  • Publication number: 20190067965
    Abstract: A separable mobile power source bracket is provided. The mobile power source is composed of a large edge external case, a small edge external case, a charging battery and a circuit module. Both the large edge external case and the small edge external case can be assembled into a completely external case through magnetic suction. The charging battery is accommodated inside the back surface case of the large edge external case. The external case can be provided for accommodating a mobile phone for protection. When the small edge external case is held and detached by imposing force, the small edge external case is peeled off the top surface of the large edge external case to lean the bottom surface of the small edge external case against the back surface of the large edge external case so that the mobile phone is at a tilt angle.
    Type: Application
    Filed: September 18, 2017
    Publication date: February 28, 2019
    Inventors: Yao-Te Liang, Jui-Shu Lin, Shu-Er Liang, Sheng-Chi Liang
  • Publication number: 20190013564
    Abstract: A multi-band antenna structure includes a substrate having a first wiring area located on one side surface thereof. The first wiring area has a first metal trace, a second metal trace and a connecting portion formed therein. The first and the second metal trace are respectively in an elongated spiral pattern; and the connecting portion is electrically connected at two opposite ends to the first and the second metal trace. The multi-band antenna structure can be directly integrated into electrical circuits on a circuit board to provide the advantages of reduced manufacturing cost and capable of transmitting or receiving multiple bands of signals.
    Type: Application
    Filed: July 6, 2017
    Publication date: January 10, 2019
    Inventors: Yang-Te Liang, Po-Wei Chiu, Sheng-Ruei Hsu, Wei-Cheng Lin, Chien-Jen Hsiao, Shih-Hsiu Tseng
  • Patent number: 10175521
    Abstract: The invention provides an optical composite layer structure with a built-in touch sensitive polymer dispersed liquid crystal (PDLC) structure. The optical composite layer structure comprises an upper transparent substrate, a lower transparent substrate, an upper transparent conductive layer, a lower transparent conductive layer and a PDLC layer. A PDLC circuit and a touch sensitive circuit are provided on the upper and lower transparent conductive layers. A cable region that is electrically connected to external soft circuit cables is provided at an end of the upper transparent conductive layer and the lower transparent conductive layer to electrically connect to an external control unit. With a touch sensitive operation of a touch sensitive circuit of the optical composite layer structure, a signal instruction is provided to the control unit. The corresponding PDLC circuit may drive the corresponding regions of PDLC layer to conduct the change of light transmission of local region.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: January 8, 2019
    Assignee: NANOBIT TECH. CO., LTD.
    Inventors: Te-Fong Chan, Fu-Tien Ku, Shiou-Ming Liu, Yu-Yang Chang, Te-Liang Yu
  • Patent number: 10071605
    Abstract: A specific multi-band antenna impedance matching circuit and a tire-pressure monitoring device using same are disclosed. The antenna impedance matching circuit includes at least one first, one second and one third inductance unit and at least one first, one second and one third capacitance unit. The first capacitance unit is connected at a first end to first ends of the first and the second inductance unit and at a second end to a ground; the second inductance unit and the second capacitance unit are connected in series; the third inductance unit and the third capacitance unit are connected in parallel; and the third inductance unit is connected at a first end to a first end of the second capacitance unit and at a second end to the ground.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: September 11, 2018
    Assignee: KEYCORE TECHNOLOGY CORP.
    Inventors: Yang-Te Liang, Po-Wei Chiu, Sheng-Ruei Hsu, Wei-Cheng Lin, Chien-Jen Hsiao, Shih-Hsiu Tseng
  • Patent number: 10036916
    Abstract: The invention provides an optical composite layer structure with a built-in touch sensitive polymer dispersed liquid crystal (PDLC) structure. The optical composite layer structure comprises an upper transparent substrate, a lower transparent substrate, an upper transparent conductive layer, a lower transparent conductive layer and a PDLC layer. A PDLC circuit and a touch sensitive circuit are provided on the upper and lower transparent conductive layers. A cable region that is electrically connected to external soft circuit cables is provided at an end of the upper transparent conductive layer and the lower transparent conductive layer to electrically connect to an external control unit. With a touch sensitive operation of a touch sensitive circuit of the optical composite layer structure, a signal instruction is provided to the control unit. The corresponding PDLC circuit may drive the corresponding regions of PDLC layer to conduct the change of light transmission of local region.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 31, 2018
    Assignee: NANOBIT TECH. CO., LTD.
    Inventors: Te-Fong Chan, Fu-Tien Ku, Shiou-Ming Liu, Yu-Yang Chang, Te-Liang Yu
  • Patent number: 10032770
    Abstract: A multi-layered semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor layer, a first insulator layer, a second semiconductor layer, a second insulator layer, and a third semiconductor layer are formed over a substrate. A first transistor comprises the first semiconductor layer, the first insulator layer, and the second semiconductor layer, and a second transistor comprises the second semiconductor layer, the second insulator layer, and the third semiconductor layer.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: July 24, 2018
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Chi-Te Liang, Minghwei Hong, Fan-Hung Liu
  • Publication number: 20180067346
    Abstract: The invention provides an optical composite layer structure with a built-in touch sensitive polymer dispersed liquid crystal (PDLC) structure. The optical composite layer structure comprises an upper transparent substrate, a lower transparent substrate, an upper transparent conductive layer, a lower transparent conductive layer and a PDLC layer. A PDLC circuit and a touch sensitive circuit are provided on the upper and lower transparent conductive layers. A cable region that is electrically connected to external soft circuit cables is provided at an end of the upper transparent conductive layer and the lower transparent conductive layer to electrically connect to an external control unit. With a touch sensitive operation of a touch sensitive circuit of the optical composite layer structure, a signal instruction is provided to the control unit. The corresponding PDLC circuit may drive the corresponding regions of PDLC layer to conduct the change of light transmission of local region.
    Type: Application
    Filed: November 1, 2017
    Publication date: March 8, 2018
    Inventors: Te-Fong CHAN, Fu-Tien KU, Shiou-Ming LIU, Yu-Yang CHANG, Te-Liang YU
  • Publication number: 20180067347
    Abstract: The invention provides an optical composite layer structure with a built-in touch sensitive polymer dispersed liquid crystal (PDLC) structure. The optical composite layer structure comprises an upper transparent substrate, a lower transparent substrate, an upper transparent conductive layer, a lower transparent conductive layer and a PDLC layer. A PDLC circuit and a touch sensitive circuit are provided on the upper and lower transparent conductive layers. A cable region that is electrically connected to external soft circuit cables is provided at an end of the upper transparent conductive layer and the lower transparent conductive layer to electrically connect to an external control unit. With a touch sensitive operation of a touch sensitive circuit of the optical composite layer structure, a signal instruction is provided to the control unit. The corresponding PDLC circuit may drive the corresponding regions of PDLC layer to conduct the change of light transmission of local region.
    Type: Application
    Filed: November 1, 2017
    Publication date: March 8, 2018
    Inventors: Te-Fong CHAN, Fu-Tien KU, Shiou-Ming LIU, Yu-Yang CHANG, Te-Liang YU
  • Patent number: 9851596
    Abstract: The invention provides an optical composite layer structure with a built-in touch sensitive polymer dispersed liquid crystal (PDLC) structure. The optical composite layer structure comprises an upper transparent substrate, a lower transparent substrate, an upper transparent conductive layer, a lower transparent conductive layer and a PDLC layer. A PDLC circuit and a touch sensitive circuit are provided on the upper and lower transparent conductive layers. A cable region that is electrically connected to external soft circuit cables is provided at an end of the upper transparent conductive layer and the lower transparent conductive layer to electrically connect to an external control unit. With a touch sensitive operation of a touch sensitive circuit of the optical composite layer structure, a signal instruction is provided to the control unit. The corresponding PDLC circuit may drive the corresponding regions of PDLC layer to conduct the change of light transmission of local region.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: December 26, 2017
    Assignee: NANOBIT TECH. CO., LTD.
    Inventors: Te-Fong Chan, Fu-Tien Ku, Shiou-Ming Liu, Yu-Yang Chang, Te-Liang Yu
  • Patent number: 9780106
    Abstract: A memory device includes an N-channel transistor and a P-channel transistor. A word line is electrically connected to a drain terminal of the N-channel transistor, and a source terminal of the P-channel transistor. A first bit line is electrically connected to a source terminal of the N-channel transistor. A second bit line is electrically connected to a drain terminal of the P-channel transistor. Gate terminals of the N-channel transistor and the P-channel transistor are electrically connected and floating.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Liang Lee, Chin-Yuan Ko, Ming-Yih Wang
  • Patent number: 9753333
    Abstract: A method for fabricating liquid crystal display panels. The method includes forming at least one adhesive structure on a first substrate, to partition the first substrate into at least one dummy region and panel group regions, in which the dummy region is located between the two adjacent panel group regions; pouring liquid crystal into the dummy region and the panel group regions; and conjugating a second substrate at a side of the first substrate disposed with the adhesive structure, to seal spaces of the dummy region and the panel group regions between the first substrate and the second substrate, in which the liquid crystal can fill up the spaces of the panel group regions and at least a part of the spaces of the dummy region being sealed between the first substrate and the second substrate.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: September 5, 2017
    Assignee: CHUNGWAI PICTURE TUBES, LTD.
    Inventors: Wei-Yen Chen, Yu-Chun Tsai, Yuan-Chieh Hsu, Te-Liang Liu, Min-Cheng Wang
  • Patent number: D1024460
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: April 23, 2024
    Assignee: PLANDDO CO., LTD.
    Inventors: Tsung-Te Sun, Chao-Shun Liang, Chia-Hsin Wu, Ping-Yun Su, Yu-Huai Yang