Patents by Inventor TE-MING KUNG
TE-MING KUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230375330Abstract: A method of evaluating a thickness of a film on a substrate includes detecting atomic force responses of the film to exposure of electromagnetic radiation in the infrared portion of the electromagnetic spectrum. The use of atomic force microscopy to evaluate thicknesses of thin films avoids underlayer noise commonly encountered when optical metrology techniques are utilized to evaluate film thicknesses. Such underlayer noise adversely impacts the accuracy of the thickness evaluation.Type: ApplicationFiled: July 28, 2023Publication date: November 23, 2023Inventors: Chih Hung CHEN, Kei-Wei CHEN, Te-Ming KUNG
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Patent number: 11761751Abstract: A method of evaluating a thickness of a film on a substrate includes detecting atomic force responses of the film to exposure of electromagnetic radiation in the infrared portion of the electromagnetic spectrum. The use of atomic force microscopy to evaluate thicknesses of thin films avoids underlayer noise commonly encountered when optical metrology techniques are utilized to evaluate film thicknesses. Such underlayer noise adversely impacts the accuracy of the thickness evaluation.Type: GrantFiled: June 22, 2022Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih Hung Chen, Kei-Wei Chen, Te-Ming Kung
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Publication number: 20230230846Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.Type: ApplicationFiled: March 15, 2023Publication date: July 20, 2023Inventors: Yi-Sheng LIN, Chi-Jen LIU, Chi-Hsiang SHEN, Te-Ming KUNG, Chun-Wei HSU, Chia-Wei HO, Yang-Chun CHENG, William Weilun HONG, Liang-Guang CHEN, Kei-Wei CHEN
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Publication number: 20230154985Abstract: A method of forming a semiconductor structure includes following operations. A substrate including a silicon (Si) layer is received. An amorphous germanium (Ge) layer is formed on the Si layer. A barrier layer is formed over the amorphous Ge layer. The substrate is annealed to transform the Si layer and the Ge layer to form a single crystalline SiGe layer. A Ge concentration is in a positive correlation with a ratio of a thickness of the Ge layer and a thickness of the Si layer.Type: ApplicationFiled: January 13, 2022Publication date: May 18, 2023Inventors: TE-MING KUNG, YING-LANG WANG, KEI-WEI CHEN, WEN-HSI LEE, SHU WEI CHANG
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Patent number: 11637021Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.Type: GrantFiled: May 18, 2021Date of Patent: April 25, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Sheng Lin, Chi-Jen Liu, Chi-Hsiang Shen, Te-Ming Kung, Chun-Wei Hsu, Chia-Wei Ho, Yang-Chun Cheng, William Weilun Hong, Liang-Guang Chen, Kei-Wei Chen
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Publication number: 20220316861Abstract: A method of evaluating a thickness of a film on a substrate includes detecting atomic force responses of the film to exposure of electromagnetic radiation in the infrared portion of the electromagnetic spectrum. The use of atomic force microscopy to evaluate thicknesses of thin films avoids underlayer noise commonly encountered when optical metrology techniques are utilized to evaluate film thicknesses. Such underlayer noise adversely impacts the accuracy of the thickness evaluation.Type: ApplicationFiled: June 22, 2022Publication date: October 6, 2022Inventors: Chih Hung CHEN, Kei-Wei CHEN, Te-Ming KUNG
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Patent number: 11397078Abstract: A method of evaluating a thickness of a film on a substrate includes detecting atomic force responses of the film to exposure of electromagnetic radiation in the infrared portion of the electromagnetic spectrum. The use of atomic force microscopy to evaluate thicknesses of thin films avoids underlayer noise commonly encountered when optical metrology techniques are utilized to evaluate film thicknesses. Such underlayer noise adversely impacts the accuracy of the thickness evaluation.Type: GrantFiled: March 8, 2021Date of Patent: July 26, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih Hung Chen, Kei-Wei Chen, Te-Ming Kung
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Publication number: 20210364275Abstract: A method of evaluating a thickness of a film on a substrate includes detecting atomic force responses of the film to exposure of electromagnetic radiation in the infrared portion of the electromagnetic spectrum. The use of atomic force microscopy to evaluate thicknesses of thin films avoids underlayer noise commonly encountered when optical metrology techniques are utilized to evaluate film thicknesses. Such underlayer noise adversely impacts the accuracy of the thickness evaluation.Type: ApplicationFiled: March 8, 2021Publication date: November 25, 2021Inventors: Chih Hung CHEN, Kei-Wei CHEN, Te-Ming KUNG
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Publication number: 20210272818Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.Type: ApplicationFiled: May 18, 2021Publication date: September 2, 2021Inventors: Yi-Sheng LIN, Chi-Jen LIU, Chi-Hsiang SHEN, Te-Ming KUNG, Chun-Wei HSU, Chia-Wei HO, Yang-Chun CHENG, William Weilun HONG, Liang-Guang CHEN, Kei-Wei CHEN
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Patent number: 11037799Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.Type: GrantFiled: May 1, 2019Date of Patent: June 15, 2021Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Yi-Sheng Lin, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, Te-Ming Kung, William Weilun Hong, Chi-Hsiang Shen, Chia-Wei Ho, Chun-Wei Hsu, Yang-Chun Cheng
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Publication number: 20200341926Abstract: An electronic apparatus installed with non-volatile memory express solid state disks (NVMe SSDs) is provided. The electronic apparatus includes a processor, a board management controller (BMC), a micro-controller, at least one first input and output (IO) expander, and a plurality of NVMe SSDs. The micro-controller is coupled to the processor and the BMC. The first IO expander is coupled between the micro-controller and the NVMe SSDs. The micro-controller reads a PRSNT # information and an IFDET # information of each of the NVMe SSDs through the first IO expander, and transmits the PRSNT # information and the IFDET # information of each of the NVMe SSDs to the processor and the BMC.Type: ApplicationFiled: October 4, 2019Publication date: October 29, 2020Applicant: COMPAL ELECTRONICS, INC.Inventors: Chang-Yu Tu, Te-Ming Kung, Wen-Shyan Lai
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Publication number: 20200098591Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.Type: ApplicationFiled: May 1, 2019Publication date: March 26, 2020Inventors: Yi-Sheng Lin, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, Te-Ming Kung, William Weilun Hong, Chi-Hsiang Shen, Chia-Wei Ho, Chun-Wei Hsu, Yang-Chun Cheng
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Publication number: 20180156552Abstract: A thermal simulation system adapted to establish a test environment for a thermal test is provided. The thermal simulation system includes a communication element, a controllable loading element, a plurality of connectors, and a controller. The communication element is configured to receive at least one of a heating control signal, a fan control signal, and a loading control signal from an external electronic device. The controllable loading element is configured to provide a loading. The connectors are configured to connect a heating element and a fan. The controller is configured to control a heat energy generated by the heating element according to the heating control signal, control a fan speed of the fan according to the fan control signal, and control a loading value of the loading provided by the controllable loading element according to the loading control signal.Type: ApplicationFiled: December 5, 2017Publication date: June 7, 2018Applicant: COMPAL ELECTRONICS, INC.Inventors: Chang-Yu Tu, Te-Ming Kung, Wen-Shyan Lai, Tung-Hua Wu
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Publication number: 20170168964Abstract: A hard drive disk indicator processing apparatus includes first and second processors. The first processor includes first, second and third communication interfaces. The first communication interface receives at least one serial general purpose input/output signal from a motherboard. The second communication interface receives a plurality piece of hard drive disk status information for responding to a plurality of hard drive disk statuses of hard drive disks. The third communication interface outputs serial information. The second processor includes fourth and fifth communication interfaces. The fourth communication interface is coupled to the third communication interface and receives the serial information. The fifth communication interface is coupled to a plurality of hard drive disk indicators. The first processor generates the serial information according to the at least one serial general purpose input/output signal.Type: ApplicationFiled: December 9, 2016Publication date: June 15, 2017Inventors: Te-Ming Kung, Chang-Yu Tu, Wen-Shyan Lai
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Patent number: 9502647Abstract: A resistive memory cell is disclosed. The resistive memory cell comprises a pair of electrodes and a resistance-switching network disposed between the pair of electrodes. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer. The group-IV doping layer comprises silicon oxide doped with a group-IV element. The porous low-k layer comprises porous silicon oxide or porous hafnium oxide. The group-IV element may comprise zirconium, titanium, or hafnium. The porous low-k layer may be prepared by inductively coupled plasma (ICP) treatment. A method of fabricating a resistive memory is disclosed. The method comprises forming a resistance-switching network on a first electrode using sputtering and forming a second electrode on the resistance-switching network using sputtering. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer.Type: GrantFiled: May 28, 2014Date of Patent: November 22, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ting-Chang Chang, Kuan-Chang Chang, Tsung-Ming Tsai, Chih-Hung Pan, Ying-Lang Wang, Kei-Wei Chen, Shih-Chieh Chang, Te-Ming Kung
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Patent number: 9368394Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a semiconductor substrate; forming a conductive region at least partially in the semiconductor substrate; forming a dielectric layer over the substrate; forming a hard mask over the dielectric layer, the hard mask having an opening over the conductive region; dry etching the dielectric layer by a first etching gas to form a recessed feature, wherein a surface of the conductive region is therefore exposed at a bottom of the recessed feature, and a byproduct film is formed at an inner surface of the recessed feature; and dry etching the dielectric layer by a second etching gas, wherein the second etching gas chemically reacts with the byproduct film and the conductive region, and a sacrificial layer is therefore built up around the bottom of the recessed feature.Type: GrantFiled: March 31, 2015Date of Patent: June 14, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Li Hung, Te-Ming Kung, Chih-Hao Chen, Kei-Wei Chen, Ying-Lang Wang, Hung Jui Chang, Horng-Huei Tseng
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Patent number: 9281475Abstract: A resistive memory cell is disclosed. The resistive memory cell comprises a pair of electrodes and a multi-layer resistance-switching network disposed between the pair of electrodes. The multi-layer resistance-switching network comprises a pair of carbon doping layers and a group-IV element doping layer disposed between the pair of carbon doping layers. Each carbon doping layer comprises silicon oxide doped with carbon. The group-IV doping layer comprises silicon oxide doped with a group-IV element. A method of fabricating a resistive memory cell is also disclosed. The method comprises forming a first carbon doping layer on a first electrode using sputtering, forming a group-IV element doping layer on the first carbon doping layer using sputtering, forming a second carbon doping layer on the group-IV element doping layer using sputtering, and forming a second electrode on the second carbon doping layer using sputtering.Type: GrantFiled: May 28, 2014Date of Patent: March 8, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ting-Chang Chang, Kuan-Chang Chang, Tsung-Ming Tsai, Chih-Hung Pan, Ying-Lang Wang, Kei-Wei Chen, Shih-Chieh Chang, Te-Ming Kung
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Publication number: 20150349251Abstract: A resistive memory cell is disclosed. The resistive memory cell comprises a pair of electrodes and a resistance-switching network disposed between the pair of electrodes. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer. The group-IV doping layer comprises silicon oxide doped with a group-IV element. The porous low-k layer comprises porous silicon oxide or porous hafnium oxide. The group-IV element may comprise zirconium, titanium, or hafnium. The porous low-k layer may be prepared by inductively coupled plasma (ICP) treatment. A method of fabricating a resistive memory is disclosed. The method comprises forming a resistance-switching network on a first electrode using sputtering and forming a second electrode on the resistance-switching network using sputtering. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer.Type: ApplicationFiled: May 28, 2014Publication date: December 3, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: TING-CHANG CHANG, KUAN-CHANG CHANG, TSUNG-MING TSAI, CHIH-HUNG PAN, YING-LANG WANG, KEI-WEI CHEN, SHIH-CHIEH CHANG, TE-MING KUNG
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Publication number: 20150349250Abstract: A resistive memory cell is disclosed. The resistive memory cell comprises a pair of electrodes and a multi-layer resistance-switching network disposed between the pair of electrodes. The multi-layer resistance-switching network comprises a pair of carbon doping layers and a group-IV element doping layer disposed between the pair of carbon doping layers. Each carbon doping layer comprises silicon oxide doped with carbon. The group-IV doping layer comprises silicon oxide doped with a group-IV element. A method of fabricating a resistive memory cell is also disclosed. The method comprises forming a first carbon doping layer on a first electrode using sputtering, forming a group-IV element doping layer on the first carbon doping layer using sputtering, forming a second carbon doping layer on the group-IV element doping layer using sputtering, and forming a second electrode on the second carbon doping layer using sputtering.Type: ApplicationFiled: May 28, 2014Publication date: December 3, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: TING-CHANG CHANG, KUAN-CHANG CHANG, TSUNG-MING TSAI, CHIH-HUNG PAN, YING-LANG WANG, KEI-WEI CHEN, SHIH-CHIEH CHANG, TE-MING KUNG