Patents by Inventor Te-Sheng Chao
Te-Sheng Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8058702Abstract: A phase change memory cell is disclosed, including a first electrode and a second electrode, and a plurality of recording layers disposed between the first and second electrodes. The phase of an active region of each of the recording layers can be changed to a crystalline state or an amorphous state by current pulse control and hence respectively has crystalline resistance or amorphous resistance. At least two of the recording layers have different dimensions such that different combinations of the crystalline and amorphous resistance result in at least three different effective resistance values between the first and second electrodes. The phase change memory cell can be realized with the same material of the recording layers and thus can be fabricated with simple and currently developed CMOS fabrication process technologies. Furthermore, the phase change memory is easy to control due to large current programming intervals.Type: GrantFiled: October 26, 2006Date of Patent: November 15, 2011Assignees: Nanya Technology Corporation, Winbond Electronics Corp.Inventor: Te-Sheng Chao
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Patent number: 8045367Abstract: A phase change memory with a primary memory array, a reference memory array, and a comparison circuit is provided. The electrical characteristic curve of the recording layers of the primary memory units is different from the electrical characteristic curve of the recording layers of the reference memory units. The primary memory array includes at least one primary memory unit to generate at least one sensing signal, wherein each of the primary memory units includes at least one recording layer can be programmed to a first resistance and a second resistance. The reference memory array includes at least one reference memory unit to generate at least one reference signal, wherein each of the reference memory units includes at least one recording layer can be programmed to change its resistance. The comparison circuit compares the sensing signal and the reference signal to generate a comparison result.Type: GrantFiled: August 8, 2008Date of Patent: October 25, 2011Assignee: Nanya Technology Corp.Inventor: Te-Sheng Chao
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Patent number: 7868314Abstract: A phase change memory device and fabricating method are provided. A disk-shaped phase change layer is buried within the insulating material. A center via and ring via are formed by a lithography. The center via is located in the center of the phase change layer and passes through the phase change layer, and the ring via takes the center via as a center. A heating electrode within the center via performs Joule heating of the phase change layer, and the contact area between the phase change layer and the heating electrode is reduced by controlling the thickness of the phase change layer. Furthermore, a second electrode within the ring via dissipates the heat transmitted to the contact interface between the phase change layers, so as to avoid transmitting the heat to the etching boundary at the periphery of the phase change layer.Type: GrantFiled: August 26, 2009Date of Patent: January 11, 2011Assignee: Industrial Technology Research InstituteInventors: Wei-Su Chen, Yi-Chan Chen, Wen-Han Wang, Hong-Hui Hsu, Chien-Min Lee, Yen Chuo, Te-Sheng Chao, Min-Hung Lee
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Patent number: 7835177Abstract: A phase change memory (PCM) cell fabricated by etching a tapered structure into a phase change layer, and planarizing a dielectric layer on the phase change layer until a tip of the tapered structure is exposed for contacting a heating electrode. Therefore, the area of the exposed tip of the phase change layer is controlled to be of an extremely small size, the contact area between the phase change layer and the heating electrode is reduced, thereby lowering the operation current.Type: GrantFiled: July 27, 2006Date of Patent: November 16, 2010Assignee: Industrial Technology Research InstituteInventors: Hong-Hui Hsu, Chien-Min Lee, Wen-Han Wang, Min-Hung Lee, Te-Sheng Chao, Yen Chuo, Yi-Chan Chen, Wei-Su Chen
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Patent number: 7773409Abstract: A writing method for a phase change memory is disclosed. The writing method inputs a first writing pulse signal to a phase change memory to heat the phase change memory to above a first temperature and inputting a second writing pulse signal to the phase change memory to keep the phase change memory at a second temperature.Type: GrantFiled: December 12, 2007Date of Patent: August 10, 2010Assignee: Industrial Technology Research InstituteInventors: Ming-Jung Chen, Te-Sheng Chao, Philip H. Yeh
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Publication number: 20100140583Abstract: A phase change memory device and fabricating method are provided. A disk-shaped phase change layer is buried within the insulating material. A center via and ring via are formed by a lithography. The center via is located in the center of the phase change layer and passes through the phase change layer, and the ring via takes the center via as a center. A heating electrode within the center via performs Joule heating of the phase change layer, and the contact area between the phase change layer and the heating electrode is reduced by controlling the thickness of the phase change layer. Furthermore, a second electrode within the ring via dissipates the heat transmitted to the contact interface between the phase change layers, so as to avoid transmitting the heat to the etching boundary at the periphery of the phase change layer.Type: ApplicationFiled: August 26, 2009Publication date: June 10, 2010Applicant: Industrial Technology Research InstituteInventors: Wei-Su Chen, Yi-Chan Chen, Wen-Han Wang, Hong-Hui Hsu, Chien-Min Lee, Yen Chuo, Te-Sheng Chao, Min-Hung Lee
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Patent number: 7679075Abstract: A phase change memory array is disclosed, comprising a first cell having a patterned phase change layer, and a second cell having a patterned phase change layer, wherein the patterned phase change layer of the first cell and the patterned phase change layer of the second cell are disposed at different layers.Type: GrantFiled: January 25, 2008Date of Patent: March 16, 2010Assignees: Industrial Technology Research Institute, Powerchip Semiconductor Corp., Nanya Technology Corporation, ProMOS Technologies Inc., Winbond Electronics Corp.Inventor: Te-Sheng Chao
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Patent number: 7660147Abstract: A programming method for a phase change memory based on the phase transformations between amorphous and crystalline phases is disclosed. The programming method comprises a current pulse with step waveform providing a first crystallization current pulse to the phase change memory and providing a second crystallization current pulse to the phase change memory. The first crystallization current pulse has a first rising edge, a first falling edge and a first peak current held for a first hold time. The second crystallization current pulse has a second peak current. The second peak current follows the first falling edge and is held for a second hold time.Type: GrantFiled: December 18, 2007Date of Patent: February 9, 2010Assignees: Industrial Technology Research Institute, Powerchip Semiconductor Corp., Nany Technology Corporation., Promos Technologies Inc., Winbond Electronics Corp.Inventors: Te-Sheng Chao, Ming-Jung Chen, Philip H. Yeh, Ming-Jinn Tsai
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Patent number: 7626191Abstract: A lateral phase change memory with spacer electrodes and method of manufacturing the same are provided. The memory is formed by connecting the conductive electrodes with lower resistivity and the spacer electrodes with higher resistivity, and filling the phase change material between the spacer electrodes. Therefore, the area that the phase change material contacts the spacer electrodes and the volume of the phase change material can be reduced; thereby the programming current and power consumption of the phase change memory are reduced.Type: GrantFiled: May 17, 2006Date of Patent: December 1, 2009Assignee: Industrial Technology Research InstituteInventors: Te-Sheng Chao, Wen-Han Wang, Min-Hung Lee, Hong-Hui Hsu, Chien-Min Lee, Yen Chuo, Yi-Chan Chen, Wei-Su Chen
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Patent number: 7598113Abstract: A phase change memory device and fabricating method are provided. A disk-shaped phase change layer is buried within the insulating material. A center via and ring via are formed by a lithography. The center via is located in the center of the phase change layer and passes through the phase change layer, and the ring via takes the center via as a center. A heating electrode within the center via performs Joule heating of the phase change layer, and the contact area between the phase change layer and the heating electrode is reduced by controlling the thickness of the phase change layer. Furthermore, a second electrode within the ring via dissipates the heat transmitted to the contact interface between the phase change layers, so as to avoid transmitting the heat to the etching boundary at the periphery of the phase change layer.Type: GrantFiled: June 30, 2006Date of Patent: October 6, 2009Assignee: Industrial Technology Research InstituteInventors: Wei-Su Chen, Yi-Chan Chen, Wen-Han Wang, Hong-Hui Hsu, Chien-Min Lee, Yen Chuo, Te-Sheng Chao, Min-Hung Lee
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Publication number: 20090065758Abstract: A phase change memory array is disclosed, comprising a first cell having a patterned phase change layer, and a second cell having a patterned phase change layer, wherein the patterned phase change layer of the first cell and the patterned phase change layer of the second cell are disposed at different layers.Type: ApplicationFiled: January 25, 2008Publication date: March 12, 2009Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, POWERCHIP SEMICONDUCTOR CORP., NANYA TECHNOLOGY CORPORATION, PROMOS TECHNOLOGIES INC., WINBOND ELECTRONICS CORP.Inventor: Te-Sheng Chao
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Publication number: 20090040820Abstract: A phase change memory with a primary memory array, a reference memory array, and a comparison circuit is provided. The electrical characteristic curve of the recording layers of the primary memory units, is different from the electrical characteristic curve of the recording layers of the reference memory units. The primary memory array includes at least one primary memory unit to generate at least one sensing signal, wherein each of the primary memory units includes at least one recording layer can be programmed to a first resistance and a second resistance. The reference memory array includes at least one reference memory unit to generate at least, one reference signal, wherein each of the reference memory units includes at least one recording layer can be programmed to change its resistance. The comparison circuit compares the sensing signal and the reference signal to generate a comparison result.Type: ApplicationFiled: August 8, 2008Publication date: February 12, 2009Applicants: ITRI, Powerchip Semiconductor Corp., Nanya Technology Corp., ProMOS Technologies Inc., Winbon Electronics Corp.Inventor: Te-Sheng Chao
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Publication number: 20080219046Abstract: A writing method for a phase change memory is disclosed. The writing method inputs a first writing pulse signal to a phase change memory to heat the phase change memory to above a first temperature and inputting a second writing pulse signal to the phase change memory to keep the phase change memory at a second temperature.Type: ApplicationFiled: December 12, 2007Publication date: September 11, 2008Inventors: Ming-Jung Chen, Te-Sheng Chao, Philip H. Yeh
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Publication number: 20080151613Abstract: A programming method for a phase change memory based on the phase transformations between amorphous and crystalline phases is disclosed. The programming method comprises a current pulse with step waveform providing a first crystallization current pulse to the phase change memory and providing a second crystallization current pulse to the phase change memory. The first crystallization current pulse has a first rising edge, a first falling edge and a first peak current held for a first hold time. The second crystallization current pulse has a second peak current. The second peak current follows the first falling edge and is held for a second hold time.Type: ApplicationFiled: December 18, 2007Publication date: June 26, 2008Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, POWERCHIP SEMICONDUCTOR CORP., NANYA TECHNOLOGY CORPORATION, PROMOS TECHNOLOGIES INC., WINBOND ELECTRONICS CORP.Inventors: Te-Sheng Chao, Ming-Jung Chen, Philip H. Yeh, Ming-Jinn Tsai
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Publication number: 20070291533Abstract: The invention provides a phase change memory device comprising a stacked structure disposed on a substrate. The stacked structure comprises a first electrode, a second electrode overlying the first electrode and an insulating layer interposed between the first and the second electrodes. A memory spacer is formed on part of the sidewall of the stacked structure to contact the first electrode, the insulating layer and the second electrode.Type: ApplicationFiled: June 5, 2007Publication date: December 20, 2007Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, POWERCHIP SEMICONDUCTOR CORP., NANYA TECHNOLOGY CORPORATION, PROMOS TECHNOLOGIES INC., WINBOND ELECTRONICS CORP.Inventors: Yen Chuo, Wen-Han Wang, Min-Hung Lee, Hong-Hui Hsu, Chien-Min Lee, Te-Sheng Chao, Yi-Chan Chen, Wei-Su Chen
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Publication number: 20070278538Abstract: A phase change memory cell is disclosed, including a first electrode and a second electrode, and a plurality of recording layers disposed between the first and second electrodes. The phase of an active region of each of the recording layers can be changed to a crystalline state or an amorphous state by current pulse control and hence respectively has crystalline resistance or amorphous resistance. At least two of the recording layers have different dimensions such that different combinations of the crystalline and amorphous resistance result in at least three different effective resistance values between the first and second electrodes. The phase change memory cell can be realized with the same material of the recording layers and thus can be fabricated with simple and currently developed CMOS fabrication process technologies. Furthermore, the phase change memory is easy to control due to large current programming intervals.Type: ApplicationFiled: October 26, 2006Publication date: December 6, 2007Applicants: INDUSTRIAL TECHNOLOGOY RESEARCH INSTITUTE, POWERCHIP SEMICONDUCTOR CORP., NANYA TECHNOLOGY CORPORATION, PROMOS TECHNOLOGIES INC., WINBOND ELECTRONICS CORP.Inventor: Te-Sheng Chao
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Publication number: 20070148855Abstract: A phase change memory device and fabricating method are provided. A disk-shaped phase change layer is buried within the insulating material. A center via and ring via are formed by a lithography. The center via is located in the center of the phase change layer and passes through the phase change layer, and the ring via takes the center via as a center. A heating electrode within the center via performs Joule heating of the phase change layer, and the contact area between the phase change layer and the heating electrode is reduced by controlling the thickness of the phase change layer. Furthermore, a second electrode within the ring via dissipates the heat transmitted to the contact interface between the phase change layers, so as to avoid transmitting the heat to the etching boundary at the periphery of the phase change layer.Type: ApplicationFiled: June 30, 2006Publication date: June 28, 2007Applicant: Industrial Technology Research InstituteInventors: Wei-Su Chen, Yi-Chan Chen, Wen-Han Wang, Hong-Hui Hsu, Chien-Min Lee, Yen Chuo, Te-Sheng Chao, Min-Hung Lee
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Publication number: 20070148862Abstract: A phase-change memory layer and method for manufacturing the same and a phase-change memory cell are provided. The phase-change memory layer is crystallized by adding one or more heterogeneous crystals that do not react with phase-change materials as the crystal nucleus, so as to reduce the time for transforming to the crystalline state from the amorphous state.Type: ApplicationFiled: May 22, 2006Publication date: June 28, 2007Inventors: Yi-Chan Chen, Hong-Hui Hsu, Chien-Min Lee, Yen Chuo, Te-Sheng Chao, Wen-Han Wang, Wei-Su Chen, Min-Hung Lee
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Publication number: 20070138595Abstract: A phase change memory (PCM) cell and fabricating method thereof are provided. A phase change layer is etched into a tapered structure, and then a dielectric layer on the phase change layer is planarized, until a tip of the tapered structure is exposed for contacting a heating electrode. Therefore, when the area of the exposed tip of the phase change layer is controlled to be of an extremely small size, the contact area between the phase change layer and the heating electrode is reduced; thereby the operation current is lowered.Type: ApplicationFiled: July 27, 2006Publication date: June 21, 2007Inventors: Hong-Hui Hsu, Chien-Min Lee, Wen-Han Wang, Min-Hong Lee, Te-Sheng Chao, Yen Chuo, Yi-Chan Chen, Wei-Su Chen
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Publication number: 20070120105Abstract: A lateral phase change memory with spacer electrodes and method of manufacturing the same are provided. The memory is formed by connecting the conductive electrodes with lower resistivity and the spacer electrodes with higher resistivity, and filling the phase change material between the spacer electrodes. Therefore, the area that the phase change material contacts the spacer electrodes and the volume of the phase change material can be reduced; thereby the programming current and power consumption of the phase change memory are reduced.Type: ApplicationFiled: May 17, 2006Publication date: May 31, 2007Inventors: Te-Sheng Chao, Wen-Han Wang, Min-Hung Lee, Hong-Hui Hsu, Chien-Min Lee, Yen Chuo, Yi-Chan Chen, Wei-Su Chen