Patents by Inventor Te Wang

Te Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240171180
    Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Inventors: GUO-HAU LEE, HUAI-TE WANG, CHENG-LIANG HUNG
  • Publication number: 20240169678
    Abstract: A system and a method for workplace safety management are provided. The method includes: dividing a work field corresponding to the workplace into work zones; assigning an environmental indicator to each of the work zones according to environmental data of the workplace; generating AR warning image signals according to the work zones and the environmental indicator; transmitting the AR warning image signals respectively to wearable electronic devices located in the workplace; and each of the wearable electronic devices displaying an AR warning image according to the received AR warning image signal.
    Type: Application
    Filed: March 27, 2023
    Publication date: May 23, 2024
    Inventors: Shuo-Yen CHEN, Wei-Ching WANG, Wei-Te CHEN
  • Publication number: 20240170211
    Abstract: A metal electrode of a ceramic capacitor and a method of forming the same are provided. The method includes mixing metal powders and a barium titanate organic-precursor to obtain precursor powders; adding an adhesive to the precursor powders to obtain a metal slurry; performing a molding process to the metal slurry to obtain a film material; performing a binder burn-out process to the film material to obtain a degumming film; and performing a sintering process to the degumming film to obtain the metal electrode. By mixing specific amount of barium titanate organic-precursor with the metal powders, the barium titanate metallic organic-precursor can be transformed to barium titanate in the following process, and barium titanate can be dispersed between the metals homogeneously. Therefore, electrode continuity can be increased.
    Type: Application
    Filed: February 24, 2023
    Publication date: May 23, 2024
    Inventors: Hsing-I HSIANG, Fu-Su YEN, Chi-Yuen HUANG, Chun-Te LEE, Kai-Hsun YANG, Shih-Ming WANG
  • Patent number: 11990111
    Abstract: A noise measuring device is provided. The noise measuring device includes a soundproof box, a sound receiving device, a holding device, and a driving device. The sound receiving device is disposed in the soundproof box. The holding device is disposed in the soundproof box and configured to hold a testing object. The driving device is connected with the soundproof box and configure to drive the soundproof box to rotate.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: May 21, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Sheng-Pin Su, Yuan-I Tseng, Che-Hung Lai, Chien-Yi Wang, Chuan-Te Chang
  • Publication number: 20240164109
    Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 16, 2024
    Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 11985830
    Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Cheng Yang, Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Chung-Te Lin
  • Publication number: 20240152880
    Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.
    Type: Application
    Filed: February 13, 2023
    Publication date: May 9, 2024
    Applicant: OBOOK INC.
    Inventors: Chun-Kai Wang, Chung-Han Hsieh, Chun-Jen Chen, Po-Hua Lin, Wei-Te Lin, Pei-Hsuan Weng, Mei-Su Wang, I-Cheng Lin, Cheng-Wei Chen
  • Publication number: 20240138152
    Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Feng-Cheng Yang, Meng-Han Lin, Sheng-Chen Wang, Han-Jong Chia, Chung-Te Lin
  • Patent number: 11967526
    Abstract: A method includes depositing a dielectric cap over a gate structure. A source/drain contact is formed over a source/drain region adjacent to the gate structure. A top of the dielectric cap is oxidized. After oxidizing the top of the dielectric cap, an etch stop layer is deposited over the dielectric cap and an interlayer dielectric (ILD) layer over the etch stop layer. The ILD layer and the etch stop layer are etched to form a via opening extending though the ILD layer and the etch stop layer. A source/drain via is filled in the via opening.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Te-Chih Hsiung, Peng Wang, Jyun-De Wu, Huan-Just Lin
  • Publication number: 20240119323
    Abstract: One or more embodiments of the present description provide a method and device for risk prediction of thermal runaway in LIB. The method includes: acquiring knowledge of a mechanism for thermal runaway in LIB; describing an evolution process of thermal runaway in LIB by adopting a fault tree; mapping a fault tree structure to a dynamic Bayesian network model for thermal runaway in LIB to obtain quantitative results of a risk of thermal runaway in LIB; and taking the quantitative results of a dynamic Bayesian network as inputs of a machine learning model to obtain prediction results of the risk of thermal runaway. By using the method in the present embodiment, an evolution trend of battery thermal runaway can be predicted by fusing multiple thermal runaway causes and multi-source data, and thus, the prediction results are relatively accurate.
    Type: Application
    Filed: May 17, 2023
    Publication date: April 11, 2024
    Applicant: Beijing Institute of Technology
    Inventors: Huixing MENG, Qiaoqiao YANG, Zhiming YIN, Cheng WANG, Te HAN, Jinduo XING
  • Publication number: 20240120317
    Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.
    Type: Application
    Filed: July 13, 2023
    Publication date: April 11, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Cheng-Hsiung Yang, Chien Te Chen, Cong Zhang, Ching-Chuan Hsieh, Yu-Ying Tan, Juan Zhou, Ai-wen Wang, Yih-Fran Lee, Yu-Wen Huang
  • Publication number: 20240121936
    Abstract: A method for forming a DRAM includes forming a bit line contact over the active area, forming a bit line over the bit line contact, and forming a hard mask layer over the bit line. The method includes forming a semiconductor material layer over the active area and forming a metal layer over the semiconductor material layer and the hard mask layer. The method includes removing the metal layer over the hard mask layer and exposing the top surface of the hard mask layer, and the remaining portion of the metal layer is between hard mask layers. The method includes removing a portion of the hard mask layer after exposing a portion of the hard mask layer. The method includes forming a capacitor contact conductive layer over the remaining portion of the metal layer after removing the portion of the hard mask layer.
    Type: Application
    Filed: September 25, 2023
    Publication date: April 11, 2024
    Inventor: Shou-Te WANG
  • Patent number: 11942340
    Abstract: An improved particle beam inspection apparatus, and more particularly, a particle beam inspection apparatus including an improved load lock unit is disclosed. An improved load lock system may comprise a plurality of supporting structures configured to support a wafer and a conditioning plate including a heat transfer element configured to adjust a temperature of the wafer. The load lock system may further comprise a gas vent configured to provide a gas between the conditioning plate and the wafer and a controller configured to assist with the control of the heat transfer element.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: March 26, 2024
    Assignee: ASML Netherlands B.V.
    Inventors: Jeroen Gerard Gosen, Te-Yu Chen, Dennis Herman Caspar Van Banning, Edwin Cornelis Kadijk, Martijn Petrus Christianus Van Heumen, Erheng Wang, Johannes Andreas Henricus Maria Jacobs
  • Patent number: 11937932
    Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: March 26, 2024
    Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, TUNGHAI UNIVERSITY
    Inventors: Chieh-Liang Wu, Chun-Te Huang, Cheng-Hsu Chen, Tsai-Jung Wang, Kai-Chih Pai, Chun-Ming Lai, Min-Shian Wang, Ruey-Kai Sheu, Lun-Chi Chen, Yan-Nan Lin, Chien-Lun Liao, Ta-Chun Hung, Chien-Chung Huang, Chia-Tien Hsu, Shang-Feng Tsai
  • Patent number: 11942371
    Abstract: A method comprises forming a gate dielectric cap over a gate structure; forming source/drain contacts over the semiconductor substrate, with the gate dielectric cap laterally between the source/drain contacts; depositing an etch-resistant layer over the gate dielectric cap; depositing a contact etch stop layer over the etch-resistant layer and an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etching process to form a via opening extending through the ILD layer and terminating prior to reaching the etch-resistant layer; performing a second etching process to deepen the via opening such that one of the source/drain contacts is exposed, wherein the second etching process etches the etch-resistant layer at a slower etch rate than etching the contact etch stop layer; and depositing a metal material to fill the deepened via opening.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Peng Wang, Huan-Just Lin
  • Patent number: 11940645
    Abstract: A front light module includes a reflective display device, a front light guide, and a light emitting unit plate. The front light guide plate includes a micro-structure. The micro-structure has a first angle between a surface thereof close to the light emitting unit and an upper surface of the front light guide plate. The micro-structure has a second angle between a surface thereof away from the light emitting unit and the upper surface of the front light guide plate. The micro-structure has a third angle between the surface thereof close to the light emitting unit and the surface thereof away from the light emitting unit. The first angle is within a range between 30 degrees and 60 degrees, the second angle is within a range between 30 degrees and 59 degrees, and the third angle is greater than 90 degrees.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: March 26, 2024
    Assignee: DARWIN PRECISIONS CORPORATION
    Inventors: Chun-Te Wang, Yu-Shan Shen, Yen-Lung Chen
  • Publication number: 20240094145
    Abstract: A method and system for detecting the location of a surface defect on a transparent film with respect to whether the surface defect is at a front or back surface of the film. By illuminating the surface defect with a light source from an oblique angle and capturing an image of the surface defect using a camera which is positioned along an axis where the light illuminates after unobstructedly reflected from the test surface of the film, and using the reflected light, an image of the surface defect is obtained. A computer executes an evaluation logic to determine whether the image of the defect contains any dark area. If there is a dark area present, the defect is judged to be on the front surface of the film. If there is no dark area present, the defect is judged to be on the back surface of the film.
    Type: Application
    Filed: March 27, 2023
    Publication date: March 21, 2024
    Inventors: Hsien-Te HSIAO, Hsuan-Fu WANG
  • Publication number: 20240096411
    Abstract: A method for performing memory access of a Flash cell of a Flash memory includes: performing a series of sensing operations respectively corresponding to a plurality of sensing voltages, wherein a sensing voltage of a specific sensing operation of the series of sensing operations has a sensing voltage determined according to a result of an initial sensing operation of the series of sensing operations; determining a threshold voltage of the Flash cell according to at least a digital value generated by the series of sensing operations; and using the determined threshold voltage to perform soft decoding of the Flash cell.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Applicant: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hsiao-Te Chang, Wen-Long Wang
  • Patent number: 11936388
    Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: March 19, 2024
    Assignee: M31 TECHNOLOGY CORPORATION
    Inventors: Guo-Hau Lee, Huai-Te Wang, Cheng-Liang Hung
  • Publication number: 20240086610
    Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Yen-Hung LIN, Yuan-Te HOU, Chung-Hsing WANG