Patents by Inventor Tea Seog Um

Tea Seog Um has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10016833
    Abstract: An solder ball mounter includes a stage configured to support a substrate, a ball placer head configured to provide solder balls, and a solder ball mask configured to align the solder balls with the substrate. The solder ball mask includes an upper mask layer including an upper opening having a first diameter, a middle mask layer including a middle opening having a second diameter that is larger than the first diameter, and a lower mask layer.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: July 10, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Yong Lee, Yo-Se Eum, Tea-Seog Um, Kyoung-Bok Cho, Jeong-Jin Lee
  • Patent number: 9324661
    Abstract: An aligning guide, a semiconductor package comprising an aligning guide, and a method of manufacturing a semiconductor package comprising an aligning guide are provided. The semiconductor package may comprise a circuit board and an aligning guide mounted on the circuit board. The aligning guide may have a plurality of stepped portions. A plurality of semiconductor chips may be stacked on the circuit board and engage with the stepped portions of the aligning guide. According to the disclosed semiconductor package, a large number of semiconductor chips may be stacked with high accuracy and sufficient margin. Therefore, the rate of failure and defects in the chip stacking process may be reduced and the reliability and stability of the semiconductor package may be enhanced.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: April 26, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo-Jin Kim, Young-Sik Kim, Tea-Seog Um, Yong-Dae Ha
  • Publication number: 20150279787
    Abstract: An aligning guide, a semiconductor package comprising an aligning guide, and a method of manufacturing a semiconductor package comprising an aligning guide are provided. The semiconductor package may comprise a circuit board and an aligning guide mounted on the circuit board. The aligning guide may have a plurality of stepped portions. A plurality of semiconductor chips may be stacked on the circuit board and engage with the stepped portions of the aligning guide. According to the disclosed semiconductor package, a large number of semiconductor chips may be stacked with high accuracy and sufficient margin. Therefore, the rate of failure and defects in the chip stacking process may be reduced and the reliability and stability of the semiconductor package may be enhanced.
    Type: Application
    Filed: March 30, 2015
    Publication date: October 1, 2015
    Inventors: Doo-Jin KIM, Young-Sik KIM, Tea-Seog UM, Yong-Dae HA
  • Patent number: 9013201
    Abstract: A method of testing objects and an apparatus for performing the same, the method including loading the objects into a testing unit through a loading unit; testing the objects in the testing unit and determining whether the objects are normal objects or abnormal objects; unloading the tested objects from the testing unit to an unloading unit; directly reversely loading the abnormal objects from the unloading unit into the testing unit when the objects are determined to be abnormal objects; and re-testing the abnormal objects in the testing unit.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Ho Park, Tea-Seog Um, In-Sik Kim, Suk-Lae Kim, Yoon-Oh Han
  • Publication number: 20150001278
    Abstract: An solder ball mounter includes a stage configured to support a substrate, a ball placer head configured to provide solder balls, and a solder ball mask configured to align the solder balls with the substrate. The solder ball mask includes an upper mask layer including an upper opening having a first diameter, a middle mask layer including a middle opening having a second diameter that is larger than the first diameter, and a lower mask layer.
    Type: Application
    Filed: February 3, 2014
    Publication date: January 1, 2015
    Applicants: SAMSUNG TECHWIN CO., LTD., SAMSUNG ELECTRONICS CO., LTD.
    Inventors: SEOK-YONG LEE, YO-SE EUM, TEA-SEOG UM, KYOUNG-BOK CHO
  • Publication number: 20130118956
    Abstract: A method of testing objects and an apparatus for performing the same, the method including loading the objects into a testing unit through a loading unit; testing the objects in the testing unit and determining whether the objects are normal objects or abnormal objects; unloading the tested objects from the testing unit to an unloading unit; directly reversely loading the abnormal objects from the unloading unit into the testing unit when the objects are determined to be abnormal objects; and re-testing the abnormal objects in the testing unit.
    Type: Application
    Filed: June 27, 2012
    Publication date: May 16, 2013
    Inventors: Jae-Ho PARK, Tea-Seog UM, In-Sik KIM, Suk-Lae KIM, Yoon-Oh HAN
  • Publication number: 20110042983
    Abstract: A nozzle for holding a substrate may include a nozzle head and a nozzle body. The nozzle head may provide the substrate with compressed air. The nozzle body may be connected to the nozzle head. The nozzle body may be arranged facing the semiconductor substrate. The nozzle body may have a substantially flat supporting surface which provides a uniform gap between the substrate and the nozzle body. The nozzle body may have a first passageway which allows the compressed air to pass through toward the substrate to form a vacuum between the substantially flat supporting surface and the substrate.
    Type: Application
    Filed: July 12, 2010
    Publication date: February 24, 2011
    Inventors: Jun-Hee YI, Tea-Seog Um, Byung-Soo Kim, Ki-Taik Oh, Dong-Hyeon Kim, Dong-Goon Jung, Jin-Pyo Lee, Hyun Jung Kim, Myung-Sup Han
  • Publication number: 20040262164
    Abstract: A plating method and apparatus including at least one plating bath including a plating solution used for plating at least one workpiece and a source providing a first current, wherein the first current is supplied to the plating solution when plating the at least one workpiece, and providing a second current, lower than the first current, wherein the second current is supplied to the plating solution during an interruption. The plating method and apparatus may include at least one main bath, at least one main anode, at least one auxiliary bath, at least one auxiliary anode, and/or a conveying unit. A portion of the conveying unit or the at least one workpiece may act as a cathode or anode. The plating method and apparatus may continuously expose a workpiece to a plating solution.
    Type: Application
    Filed: February 17, 2004
    Publication date: December 30, 2004
    Inventors: Sang-Hun Han, Jun Eui Lee, Do-Woo Lee, Young Cheol Choi, Tea Seog Um