Abstract: A semiconductor device package includes a semiconductor chip having a top surface on which a conductive pad is disposed, a bottom surface opposite to the top surface, and a side surface connecting the top and bottom surfaces to each other; a first insulating layer covering the top surface of the semiconductor chip and laterally extending to the outside of the semiconductor chip; a fillet member covering a boundary where the side surface of the semiconductor chip and the first insulating layer meet each other; and a molding layer covering the bottom surface of the semiconductor chip, the fillet member, and the first insulating layer.

Abstract: A method of fabricating a semiconductor chip package, in which a protection layer is formed on a scribe lane of a wafer including a plurality of semiconductor chips, an encapsulation layer is formed on the semiconductor chips and the protection layer, and at least two types of lasers having different respective wavelengths are sequentially irradiated to the scribe lane so as to separate the semiconductor chips. Therefore, the wafer can be protected from the laser that is used to saw the encapsulation layer.

Abstract: A semiconductor package and a method of manufacturing the semiconductor package are provided. A semiconductor package according to the present general inventive concept may include a base substrate having one surface on which a connection terminal is formed and a first package substrate having a molding layer covering the base substrate. The molding layer faces a circumference of the connection terminal and includes a side surface having first and second surfaces having a circumference of a different size, respectively.

Abstract: A semiconductor package and module, and methods of fabricating the same are provided. A method of fabricating a semiconductor package may include bonding rear surfaces of first and second semiconductor chips to each other, each of the semiconductor chips having chip pads exposed on front surfaces. The method may also include forming an encapsulation portion configured to encapsulate side surfaces of the bonded semiconductor chips, forming via plugs configured to pass through the encapsulation portion, forming an insulating layer configured to expose surfaces of the chip pads and the via plugs on the exposed surfaces of the two semiconductor chips and surfaces of the encapsulation portion, and forming package pads on the exposed surfaces of the chip pads and the surfaces of the via plugs.

Abstract: Provided are a semiconductor package, an electronic device including the semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package includes semiconductor chips mounted on a carrier, a first insulating layer sealing the semiconductor chips, first via-holes which are formed in the first insulating layer and expose a portion of each of the semiconductor chips, a first conductive pattern which is filled in the first via-holes and electrically connected to each of the semiconductor chips, and an external terminal which is electrically connected to the first conductive pattern. The semiconductor package is manufactured by performing an encapsulating process and a via-hole process.

Abstract: A semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. According to the present invention, even if a mechanical stress or a thermal stress is applied to an interconnection, a crack does not occur in the interconnection or the interconnection is not disconnected. Therefore, a reliability of the semiconductor package is improved.

Abstract: In one embodiment, a semiconductor package disclosed herein can be generally characterized as including a resin substrate having a first recess, a first interconnection disposed on a surface of the first recess, a first semiconductor chip disposed in the first recess, and an underfill resin layer substantially filling the first recess and covering a side surface of the first semiconductor chip. The first semiconductor chip is electrically connected to the first interconnection.

Abstract: A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other.

Abstract: In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body. The semiconductor package includes a post within the first insulating body and adjacent to a side of the first semiconductor chip.

Abstract: Provided are methods of fabricating a circuit board and a semiconductor package, and a circuit board and a semiconductor package fabricated using the methods. The circuit board comprises: a lower wiring pattern disposed on an upper surface of a resin substrate comprising a filler; a resin layer disposed on the lower wiring pattern; an upper wiring pattern comprising a bonding pad disposed on the resin layer; and a passivation layer comprising an upper opening exposing the bonding pad. The resin substrate comprises a substrate opening exposing a lower surface of the lower wiring pattern.

Abstract: A multi-chip package includes a mounting substrate, a first semiconductor chip, a second semiconductor chip, a reinforcing member, conductive wires and an encapsulant. The first semiconductor chip is disposed on the mounting substrate. The second semiconductor chip is disposed on the first semiconductor chip. An end portion of the second semiconductor chip protrudes from a side portion of the first semiconductor chip. A reinforcing member is disposed on an overlapping region of the second semiconductor chip where the second semiconductor chip overlaps with the side portion of the first semiconductor chip such that the reinforcing member decreases downward bending of the second semiconductor chip from the side portion of the first semiconductor chip. The conductive wires electrically connect the first and second semiconductor chips to the mounting substrate. The encapsulant is disposed on the mounting substrate to cover the first and second semiconductor chips and the conductive wires.

Abstract: Provided are a thin semiconductor chip pickup apparatus and method for detaching a die bonding film from a semiconductor chip using the apparatus. The apparatus may include a stage for supporting a die-bonding film to which a semiconductor chip is attached, a plurality of suction members arranged on the center of the stage for extracting the die-bonding film by a vacuum, where the suction members detach the die-bonding film away from the semiconductor chip to form a vacuum region, and a plurality of vacuum suction ports respectively interposed between adjacent suction members to allow the suction members to detach the die-bonding film by the vacuum.