Patents by Inventor Teck Ee Guan

Teck Ee Guan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power reduction for system on chip
    Patent number: 8510547
    Abstract: Disclosed herein are SOC devices with peripheral units having power management logic.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: August 13, 2013
    Assignee: Intel Corporation
    Inventors: Teck Ee Guan, Kai Hoong Fong
  • POWER REDUCTION FOR SYSTEM ON CHIP
    Publication number: 20110258469
    Abstract: Disclosed herein are SOC devices with peripheral units having power management logic.
    Type: Application
    Filed: June 24, 2011
    Publication date: October 20, 2011
    Inventors: Teck Ee Guan, Kai Hoong Fong
  • Power reduction for system on chip
    Patent number: 7991992
    Abstract: Disclosed herein are SOC devices with peripheral units having power management logic.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventors: Teck Ee Guan, Kai Hoong Fong
  • Power reduction for system on chip
    Publication number: 20080229130
    Abstract: Disclosed herein are SOC devices with peripheral units having power management logic.
    Type: Application
    Filed: March 13, 2007
    Publication date: September 18, 2008
    Inventors: Teck Ee Guan, Kai Hoong Fong
  • Anti-lock CPU clock control method, circuit and apparatus
    Patent number: 5789952
    Abstract: The present invention provides power saving features that can be used in a computer or other device employing an internal clock to dynamically change the frequency at which the clock operates to respond to demands upon system resources. For example, the CPU clock in the synchronous logic core may be changed dynamically to reduce power consumption without causing a CPU lock-up. A PLL clock internal to the CPU has a reduced sensitivity to external clock changes. The present invention provides a means to incrementally change the internal clock frequency by intermittently stopping the output of the internal clock.
    Type: Grant
    Filed: May 1, 1996
    Date of Patent: August 4, 1998
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kok-Kean Yap, Teck-Ee Guan