Abstract: Method for creating gates and circuits for computing apparatus with greatly improved characteristics of size, weight, power consumption, reliability, environmental tolerance, radiation hardiness, and operational speed at reduced costs by using symbol transformer, is provided. The symbol transformer having at least a first multiplicity of symbol ports coupled to a first variety of symbols, and a second multiplicity of symbol ports coupled to a second variety of symbols, associates an arbitrary one or plurality of the first multiplicity of symbol ports to and with any one or any plurality of the second or other multiplicities of symbol ports. The symbols represent static, dynamic, or both type of variables, and are used to operations of reversible, irreversible, randomized and quantum gates, circuits, and apparatus. Examples of code-controlled symbol transformer circuits embodiments demonstrate amenability for down scaling and manufacturing in silicon and other main-line processings.

Abstract: Method and machine for storing massive amounts of information in very small spaces; and for combining that with the characteristics of very high speed program, write and read operations, small power consumption, great environmental tolerance, radiation hardness and reliability, small size and weight, at low costs, are provided. The method associates, couples and transforms content symbol and address symbol to each other, stores and memorizes the associations, couplings and transforms, by and in a symbol transformer machine. The first augmentation dissects the symbol into symbol parts, operates on and with symbol parts, and combines symbol parts. The second augmentation operates on and with polyadic numbers and polyadic number parts. The third and fourth augmentations comprise conversions and auxiliary storage of symbols and symbol parts, respectively.

Abstract: A high performance fault tolerant orthogonal shuffle memory comprising a plurality of memory cells arranged to form a two-dimensional array of rows and columns. Each memory cell includes a data store element for storing data and a multi-state data transmission element to provide access to the data stored in the data store element. Each memory cell has the dual function of storing and transmitting (i.e. shifting) data. The memory cell array is coupled to first and second registers and a shuffle signal generator. In operation, data is shuffled column by column through the array, such that only two columns of memory cells are activated at any time. The shuffle memory herein disclosed may form subarrays of each of a data storage array and a redundancy storage array that are coupled to an improved error detector and corrector to form a high performance fault tolerant orthogonal memory system.

Abstract: Static content addressable memory cells (CAMs) combining six transistors and two pairs of control signal lines, where both pairs of lines provide dual functions and where the content addressing function is provided by a unique combination of control and precharge signals on the four control signal lines. An alternate CAM embodiment comprising eight transistors and an additional interrogation signal line is also disclosed. The disclosed content addressable memory cells are preferably implemented by complementary metal oxide field effect transistors (CMOSFETs) and have particular application in very large scale integrated (VLSI) chips, where small cell size is of high importance and/or where high operational speed, reliability, radiation hardness and/or noise immunity, and/or operation at high temperatures and/or a large supply voltage range is required.

Abstract: A voltage generator circuit for producing an output voltage which tracks the threshold voltage variation of the MOS devices on the semiconductor body, the magnitude of the output voltage being equal to or slightly greater than the absolute magnitude of the threshold voltages. The circuit includes two MOSFETs having their conduction paths connected in electrical series, each MOSFET having an applied gate-to-source voltage of 2V.sub.T. The voltage output terminal is connected to the node between the series connected conduction path terminals of the first and second MOSFETs. Three series connected MOSFETs which form a source follower circuit are also provided for providing the required gate-to-source voltage on the first two MOSFETs.

Abstract: A high performance sense amplifier that is preferably fabricated from complementary metal oxide semiconductor field effect transistors (CMOSFETs) and is especially suited for applications in a radiation hardened environment. The sense amplifier of the present invention is characterized by high sensitivity, high gain, good noise immunity, low power dissipation, fast operation, relatively small geometrical size, and good stabilization for temperature and supply effects while providing self-compensation for non-uniformities of electrical parameters which may occur as the result of MOS device processing or exposure to a nuclear radiation event.

Abstract: A digital scanning system for a digital to analog converter. The scanning system includes an information counter for storing a plurality of digital bits I1, I2, I3....IN, with bit I1 being the most significant bit and bit IN being the least significant bit. Logic gates are connected between the information and interconnected shift registers. A clock applies clock frequency signals to the shift registers such that the digital bits are output in the periodic sequence I1, I2, I1, I3, I1, I2, I1, I4, I1, I2, I1, I3, I1...I1, I2, I1, IN. The periodic sequence of digital bits is applied to an integrator which outputs a voltage level representative of the periodic sequence.