Patents by Inventor Tei TO
Tei TO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Particle beam apparatus, defect repair method, lithographic exposure process and lithographic system
Patent number: 11996267Abstract: A particle beam apparatus includes an object table configured to hold a semiconductor substrate; a particle beam source configured to generate a particle beam; a detector configured to detect a response of the substrate caused by interaction of the particle beam with the substrate and to output a detector signal representative of the response; and a processing unit configured to: receive or determine a location of one or more defect target areas on the substrate; control the particle beam source to inspect the one or more defect target areas; identify one or more defects within the one or more defect target areas, based on the detector signal obtained during the inspection of the one or more defect target areas; control the particle beam source to repair the one or more defects.Type: GrantFiled: August 22, 2019Date of Patent: May 28, 2024Assignee: ASML NETHERLANDS B.V.Inventors: Ruben Cornelis Maas, Alexey Olegovich Polyakov, Teis Johan Coenen -
Patent number: 11990550Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a S/D silicide layer formed on the S/D epitaxial layer, and the S/D silicide layer has a first width, the S/D epitaxial layer has a second width, and the first width is smaller than the second width. The semiconductor structure includes a dielectric spacer between the gate structure and the S/D silicide layer, and a top surface of the dielectric spacer is lower than a top surface of the gate structure.Type: GrantFiled: December 9, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Chieh Wang, Yu-Ting Lin, Yueh-Ching Pai, Shih-Chieh Chang, Huai-Tei Yang
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Patent number: 11984252Abstract: A winding-type coil component includes a first wire and a second wire having a twisted wire portion where the first wire and the second wire are twisted together. Switching positions of the first wire and the second wire in the twisted wire portion are shifted in a circumferential direction of a winding core portion every turn.Type: GrantFiled: December 28, 2020Date of Patent: May 14, 2024Assignee: Murata Manufacturing Co., Ltd.Inventors: Kohei Kobayashi, Ryota Hashimoto, Hiroyuki Tei, Chihiro Yamaguchi
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Patent number: 11978516Abstract: A memory system having a dynamic supply voltage to sense amplifiers. The supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.Type: GrantFiled: April 11, 2022Date of Patent: May 7, 2024Assignee: SanDisk Technologies LLCInventors: Yanjie Wang, Ohwon Kwon, Kou Tei, Tai-Yuan Tseng, Yasue Yamamoto, Yonggang Wu, Guirong Liang
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Publication number: 20240141337Abstract: RNA molecules for RNA interference to target a mutant allele with a point mutation, wherein the molecule has a nucleotide sequence complementary to a nucleotide sequence of a coding region of the mutant allele; and when counted from the base at the 5?-end in the nucleotide sequence complementary to the sequence of the mutant allele: a base at position 5 or 6 is mismatched with a base in the mutant allele; a base at position 10 or 11 is at the position of the point mutation and is identical to the base at the position of the point mutation in the mutant allele; the group at the 2?-position of the pentose in the ribonucleotide at position 8 is modified with OCH3, halogen, or LNA; and the group at the 2?-position of the pentose in the ribonucleotide at position 7 is not modified with any of OCH3, halogen, and LNA.Type: ApplicationFiled: January 17, 2022Publication date: May 2, 2024Applicant: THE UNIVERSITY OF TOKYOInventors: Kumiko UI-TEI, Yoshiaki KOBAYASHI, Atsushi SATO, Yoshimasa ASANO, Yuria SUZUKI, Naomi LEDEY, Kaoru SAIGO, Yukikazu NATORI
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Patent number: 11973127Abstract: Semiconductor structures and method for forming the same are provide. The semiconductor structure includes a fin structure protruding from a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes an Arsenic-doped region formed in the fin structure and a source/drain structure formed over the Arsenic-doped region. In addition, a bottommost portion of the Arsenic-doped region is lower than a bottommost portion of the source/drain structure.Type: GrantFiled: November 4, 2020Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee, Huai-Tei Yang
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Patent number: 11963986Abstract: The application discloses Lactobacillus strains having a beneficial effect on the metabolic health on a mammalian subject. Further disclosed is compositions comprising such strains and the use thereof for improving the metabolic health or for lowering the blood glucose level in a mammalian subject.Type: GrantFiled: October 24, 2019Date of Patent: April 23, 2024Assignee: Novozymes A/SInventors: Nanna Ny Kristensen, Alexandra Mattern, Delphine Marie Anne Saulnier, Jeffrey Schultchen, Teis Jensen, Benjamin Anderschou Holbech Jensen
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Patent number: 11966628Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.Type: GrantFiled: June 2, 2022Date of Patent: April 23, 2024Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wei-Chen Wang, Han-Wen Hu, Yung-Chun Li, Huai-Mu Wang, Chien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo
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Publication number: 20240122553Abstract: A brainwave auscultation method includes steps: providing a brainwave auscultation device; placing a brainwave pickup unit of the brainwave auscultation device on the head of a testee to acquire a primitive brainwave signal of the testee, and transmitting the primitive brainwave signal to a signal processing unit; the signal processing unit filtering the primitive brainwave signal according to a waveband reservation standard to generate a preparatory signal, wherein wavebands reserved by the waveband reservation standard include a ? waveband, a ? waveband, an ? waveband, a ? waveband, and a ? waveband; the signal processing unit shifting a central frequency of the preparatory signal to an audible range of human ears; the signal processing unit performing spread-spectrum operation to the shifted preparatory signal to generate a pre-vocalization signal whose frequencies range from 20 Hz to 20 kHz; and making a loudspeaker generate sounds based on the pre-vocalization signal.Type: ApplicationFiled: October 18, 2022Publication date: April 18, 2024Applicant: National Taipei University of TechnologyInventors: Ren-Guey LEE, Tei-Wei HUNG
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Publication number: 20240055175Abstract: First and second wires form a wire assembly by being wound around a winding core portion together. The wire assembly includes a twisted wire portion, an inner layer portion, an outer layer portion, a plurality of outward transition portions, and an inward transition portion. The outer layer portion includes a first outer layer portion which is connected to one of the outward transition portions extending from an intermediate position of the inner layer portion and connected to the inward transition portion. The inward transition portion extends to an intermediate position of the inner layer portion.Type: ApplicationFiled: October 25, 2023Publication date: February 15, 2024Applicant: Murata Manufacturing Co., Ltd.Inventors: Ryota HASHIMOTO, Atsuyoshi MAEDA, Chihiro YAMAGUCHI, Hiroyuki TEI, Kohei KOBAYASHI
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Publication number: 20240036735Abstract: An embodiment of the present disclosure discloses a memory device. The memory device comprises a memory controller, a buffer and a memory array. The buffer is coupled to the memory controller or embedded in the memory controller. A storage space of the buffer is configured by the memory controller to include a plurality of groups. The memory array is coupled to the memory controller, and comprising a plurality of tiles. The groups are one-to-one corresponding to the tiles. Each of the groups is configured to store data to be written into the corresponding tile. The memory controller performs one or more write operations based on the groups.Type: ApplicationFiled: July 26, 2022Publication date: February 1, 2024Inventors: Wei-Chen WANG, Tse-Yuan WANG, Yuan-Hao CHANG, Tei-Wei KUO
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Patent number: 11881266Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings. The memory cells are configured to retain a threshold voltage. The rows include full circle rows and semi-circle rows in which the memory holes are partially cut by a slit half etch. The memory holes of the semi-circle rows are coupled semi-circle bit lines and the memory holes of the full circle rows are coupled to full circle bit lines. A control means is configured to erase the memory cells in an erase operation. During the erase operation, the control means creates a capacitive coupling between each of the semi-circle bit lines and at least one neighboring one of the full circle bit lines to increase a semi-circle erase voltage applied to each of the semi-circle bit lines.Type: GrantFiled: February 8, 2022Date of Patent: January 23, 2024Assignee: SanDisk Technologies LLCInventors: Xiang Yang, Kou Tei, Ohwon Kwon
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Publication number: 20240006193Abstract: The semiconductor device manufacturing method includes a bonding step of bonding a wire to an electrode (35a), a looping wire formation step of looping the wire from the electrode (35a) to a dummy electrode (34) to form a looping wire (50a), a pressing step of pressing a part of the wire, a moving step of moving the pressed part of the wire directly above the electrode, a wire separation step of separating the wire partially from a wire supply to form a pin wire (55a) extending vertically upward from the electrode (35a), wherein the looping wire formation step adjusts the looping height of the wire to set the length of the looping wire to a predetermined length.Type: ApplicationFiled: November 25, 2020Publication date: January 4, 2024Applicant: SHINKAWA LTD.Inventors: Hiroaki Yoshino, Shinsuke TEI
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Patent number: 11854811Abstract: A finFET device and methods of forming are provided. The method includes etching recesses in a substrate on opposite sides of a gate stack. The method also includes epitaxially growing a source/drain region in each recess, where each of the source/drain regions includes a capping layer along a top surface of the respective source/drain region, and where a concentration of a first material in each source/drain region is highest at an interface of the capping layer and an underlying epitaxy layer. The method also includes depositing a plurality of metal layers overlying and contacting each of the source/drain regions. The method also includes performing an anneal, where after the anneal a metal silicide region is formed in each of the source/drain regions, where each metal silicide region extends through the capping layer and terminates at the interface of the capping layer and the underlying epitaxy layer.Type: GrantFiled: April 14, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Min Huang, Huai-Tei Yang, Shih-Chieh Chang
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Patent number: 11848138Abstract: A coil component includes a drum core including a winding core portion and flange portions on opposite sides of the winding core portion in its axial direction, a wire wound around the winding core portion, and a sheet core arranged on a top surface of each of the flange portions and on the wire with an adhesive interposed therebetween. The adhesive contains no filler. A shortest distance between the top surface of the flange portion and the sheet core is not smaller than about 3 ?m.Type: GrantFiled: January 9, 2019Date of Patent: December 19, 2023Assignee: Murata Manufacturing Co., Ltd.Inventor: Hiroyuki Tei
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Patent number: 11830657Abstract: First and second wires form a wire assembly by being wound around a winding core portion together. The wire assembly includes a twisted wire portion, an inner layer portion, an outer layer portion, a plurality of outward transition portions, and an inward transition portion. The outer layer portion includes a first outer layer portion which is connected to one of the outward transition portions extending from an intermediate position of the inner layer portion and connected to the inward transition portion. The inward transition portion extends to an intermediate position of the inner layer portion.Type: GrantFiled: May 12, 2021Date of Patent: November 28, 2023Assignee: Murata Manufacturing Co., Ltd.Inventors: Ryota Hashimoto, Atsuyoshi Maeda, Chihiro Yamaguchi, Hiroyuki Tei, Kohei Kobayashi
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Publication number: 20230378359Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
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Publication number: 20230365463Abstract: The present invention relates to a method for producing a chemically strengthened glass substrate, the method including the following steps (A) to (C): (A) preparing a chemically strengthened glass substrate A having a main surface and an end surface; (B) obtaining a glass substrate by polishing a surface of the chemically strengthened glass substrate A; and (C) performing ion exchange by bringing the glass substrate into contact with an inorganic salt composition including 90% by mass or more of KNO3 and 1.0% by mass or more and 6.0% by mass or less of NaNO3 to obtain a chemically strengthened glass substrate C.Type: ApplicationFiled: May 11, 2023Publication date: November 16, 2023Applicant: AGC Inc.Inventors: Kaname SEKIYA, Yusuke FUJIWARA, Akio SHIZUKAI, Seikichi TEI, Takashi ETO
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Patent number: 11817499Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.Type: GrantFiled: June 29, 2022Date of Patent: November 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
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Patent number: 11817261Abstract: An ink includes a boron-doped nanodiamond having a specific surface area of 110 m2/g or greater, and electrical conductivity at 20° C. of 5.0×10?3 S/cm or greater.Type: GrantFiled: November 18, 2021Date of Patent: November 14, 2023Assignees: DAICEL CORPORATION, TOKYO UNIVERSITY OF SCIENCE FOUNDATIONInventors: Takeshi Kondo, Tatsuo Aikawa, Makoto Yuasa, Kenjo Miyashita, Masahiro Nishikawa, Takahiro Tei