Abstract: A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is configured to include at least a consecutive segment, and each segment is configured to include at least a consecutive frame. Each frame is configured to include at least a consecutive page. Each virtual memory region is configured to include a plurality of areas, and each area is configured to include at least a virtual erase unit. The memory logical block region is configured to include a plurality of clusters, and each cluster includes at least a consecutive memory logical block.

Abstract: A highly efficient data characteristic identification method for flash memory is provided, including the steps of: (a) based on the LBA corresponding to the write request to the flash memory, finding K corresponding counters in the hash table through K hash functions; (b) determining whether to perform decay period computation on hash table; if so, proceeding to step (c); otherwise, proceeding to step (d); (c) performing decay period computation on the hash table; (d) performing state update computation on the hash table; and (e) checking the hash table state and determining whether the data in the logic block corresponding to the flash memory is frequently updated. The method contains the decay period computation, state update computation, and checking on the data in the corresponding counters in the hash table to determine whether the data is frequently updated. Therefore, the object of a highly efficient data access characteristic identification method for flash memory is provided.

Abstract: A highly efficient data characteristic identification device for flash memory is provided, including an instruction register, a plurality of auxiliary controllers, a data register, an address register, a microprocessor, a plurality of hash function units, a hash table unit, a comparator, a shifter, and an adder. By connecting the instruction register, data register and address register to a flash memory access control circuit and flash memory for storing the control instruction of the access control circuit and the data and physical and logical address of the flash memory, the control instruction is decoded and transmitted by the microprocessor and the auxiliary controllers to each circuit. A plurality of hash function units, a hash table unit, a comparator, a shifter, and an adder form an index computation circuit for flash memory LBA. By using the index and computation on the contents of the hash function units, the data characteristics of the LBA can be stored with less memory and higher efficiency.

Abstract: A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is configured to include at least a consecutive segment, and each segment is configured to include at least a consecutive frame. Each frame is configured to include at least a consecutive page. Each virtual memory region is configured to include a plurality of areas, and each area is configured to include at least a virtual erase unit. The memory logical block region is configured to include a plurality of clusters, and each cluster includes at least a consecutive memory logical block.

Abstract: A flash translation layer apparatus is disclosed. The flash translation layer apparatus coupled to a flash memory and a reading and writing controller, respectively. The flash translation layer apparatus includes an instruction register, a logical address register, a data register, a first auxiliary controller, a microprocessor, an address converting unit, a second auxiliary controller, a flash address register and an adjustable translation layer unit. Furthermore, the adjustable translation layer unit regards the block as a unit for a coarse-grained address translation table and regards the pages as a unit for a fine-grained address translation table, respectively. Therefore, the present invention can provide capabilities of reducing the spaces and the times of a null data collection procedure and increasing the efficiency when a logical address corresponds to a physical address.

Abstract: A method of facilitating reliably accessing flash memory is provided. During the write-in process, the present invention utilizes the steps of coding write-in data to generate extra data, and then generating the first error correction code by performing an error-correcting operation on the write-in data and the extra data. Finally, store the N write-in data and the generated K extra data into the data area and the first ECC into the spare area. During read process, the present invention utilizes the steps of reading data from the data area of the target flash-memory page to generate the second ECC, counting with the counter a number of bit differences between the first ECC and the second ECC, and selecting M data from the N write-in data and the K extra data as decoding factors to retrieve the N write-in data. The higher the counter values, the lower the likelihood the corresponding bit is selected to be retrieved.

Abstract: A cache device comprises a hard disk, cache control unit and at least one flash memory, whereby the cache control unit controlling and regulating the flash memory as the hard disk cache device. The present invention method is defined by setting up a management table to manage each corresponding logical block address of the flash memory through a cache data read-out step and cache data write-in step in order to manage the cache read or write action of the flash memory on the hard disk. In addition, the step of recycling a cache space and replacing cache temporary data storage is to remove and replace temporary cache and storage space within the flash memory on the hard disk. Moreover, the step of reconstruction management table is provided to reconstruct management table loss or damage caused by power outage or irregular shut-down of the computer and will be able to provide flash memory on the hard disk cache control.

Abstract: A method for performing a static wear leveling on a flash memory is disclosed. Accordingly, a static wear leveling unit is disposed with a block reclamation unit of either a flash translation layer or a native file system in the flash memory, and utilizes less memory space to trace a distribution status of block leveling cycles of each physical block of the flash memory. Based on the distribution record of the block leveling cycles, the number of the leveling cycles less than a premeditated threshold would be found while the system idles. Then the static wear leveling unit requests the block reclamation unit to level the found blocks. Before leveling the found block, the rarely updated data is compelled to move from one block to another block which is leveled frequently, whereby accurate wear leveling cycles for the blocks can be averaged extremely.

Abstract: A management method for reducing the utilization rate of random access memory (RAM) while reading data from or writing data to the flash memory is disclosed. A physical memory set is constructed from a plurality of physical memory blocks in the flash memory. A logical set is constructed from a plurality of logical blocks wherein the data stored in the logical set are stored in the physical memory set. Further, the data stored in each of the logical blocks are stored in one number of physical memory blocks. A mapping table is constructed and includes a hash function, a logical set table, a physical memory set table, and a set status table for managing the relationship among the physical memory sets, physical memory blocks, and logical blocks while reading data from or writing data to the flash memory.

Abstract: A caching device is positioned between a memory read/write controller and a flash memory, which contains an instruction register, a logical address register, a data register, a pair of auxiliary controllers, a microprocessor, an address translation unit, a flash memory address register, a caching control unit, and a caching instruction and data buffer area. Among them, the microprocessor is the core of the caching device responsible not only for the reading and writing the flash memory but also for the caching operation for logical and physical address translation. The caching control unit is a programmable device containing the instruction and data for caching the logical and physical address mapping. The caching instruction and data buffer area temporarily stores the caching instruction and data used by the caching control unit.

Abstract: A caching method provides a cashing mechanism between a logical addresses and a flash memory physical addresses. The cashing mechanism involves a search tree which contains a number of internal and external translation nodes. Each external translation node points to a link list of translation units, and each translation unit records a range of logical addresses and the corresponding range of physical addresses, in addition to a version value. By traversing the search tree to reach a translation unit, the physical address of a target logical address can be determined in an efficient manner. The version value of the translation unit can be used to determine the space taken up for storing the mapping of the logical and physical addresses should be released for reuse.

Abstract: An apparatus for improving the data access reliability of flash memory is provided, including an instruction register, an address register, a flash memory control circuit, a data register, an encoder, an error correction code (ECC) generator, a signal converter, a comparator, an arbitrator, and a decoder. The instruction register and the address register are connected to a flash memory respectively for storing the access instructions and the addresses. The flash memory control circuit is connected to both instruction register and address register for controlling the access to the flash memory. The data register is connected to flash memory control circuit for loading data to be written to the flash memory. The encoder encodes the written data, and the ECC generator generates an ECC, which is written to the flash memory through the signal converter. The comparator and the arbitrator provide the comparison with ECC and informing decoder f suspicious bit values when data is read from the flash memory.

Abstract: A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is configured to include at least a consecutive segment, and each segment is configured to include at least a consecutive frame. Each frame is configured to include at least a consecutive page. Each virtual memory region is configured to include a plurality of areas, and each area is configured to include at least a virtual erase unit. The memory logical block region is configured to include a plurality of clusters, and each cluster includes at least a consecutive memory logical block.

Abstract: A highly efficient data characteristic identification method for flash memory is provided, including the steps of: (a) based on the LBA corresponding to the write request to the flash memory, finding K corresponding counters in the hash table through K hash functions; (b) determining whether to perform decay period computation on hash table; if so, proceeding to step (c); otherwise, proceeding to step (d); (c) performing decay period computation on the hash table; (d) performing state update computation on the hash table; and (e) checking the hash table state and determining whether the data in the logic block corresponding to the flash memory is frequently updated. The method contains the decay period computation, state update computation, and checking on the data in the corresponding counters in the hash table to determine whether the data is frequently updated. Therefore, the object of a highly efficient data access characteristic identification method for flash memory is provided.

Abstract: A highly efficient data characteristic identification device for flash memory is provided, including an instruction register, a plurality of auxiliary controllers, a data register, an address register, a microprocessor, a plurality of hash function units, a hash table unit, a comparator, a shifter, and an adder. By connecting the instruction register, data register and address register to a flash memory access control circuit and flash memory for storing the control instruction of the access control circuit and the data and physical and logical address of the flash memory, the control instruction is decoded and transmitted by the microprocessor and the auxiliary controllers to each circuit. A plurality of hash function units, a hash table unit, a comparator, a shifter, and an adder form an index computation circuit for flash memory LBA. By using the index and computation on the contents of the hash function units, the data characteristics of the LBA can be stored with less memory and higher efficiency.