Abstract: A superscalar microprocessor implements a reorder buffer to support out-of-order execution of instructions. To reduce the time delay for identifying mispredicted instructions, prioritizing mispredicted instructions, canceling instructions subsequent to the mispredicted instruction and reading status information from the reorder buffer, the availability of an instruction tag, which identifies the instruction being executed, during the execution of the instruction is utilized. The reorder buffer receives the tag of the instruction issued to the functional unit. In parallel with the execution of the instruction, the reorder buffer generates hit masks identifying instructions to be canceled in the event of a mispredicted branch. In parallel, status information from the instruction (or instructions) being executed is selected from the reorder buffer and prioritization masks are generated.

Abstract: A superscalar microprocessor implements a reorder buffer to support out-of-order execution of instructions. The reorder buffer stores speculatively executed instructions until the instructions prior to the speculatively instruction have completed without exception. When an exception, such as a branch misprediction, occurs, the reorder buffer may cancel the instructions in the reorder buffer after the exception and restore the state of the reorder buffer to the state prior to the execution of the exception. Properly restoring the state of the reorder buffer requires instruction status information about the mispredicted branch instruction, which is stored in the reorder buffer. Additionally, if multiple branch mispredictions are detected, the mispredictions must be prioritized to determine the misprediction that occurred earliest in the program order.

Abstract: An improved signal line routing scheme includes a plurality of dynamic signal lines disposed in parallel to each other, and a plurality of static signal lines disposed in parallel to each other and also disposed in parallel with the plurality of dynamic signal lines, wherein at least one of the plurality of static signal lines is disposed immediately adjacent to each one of the plurality of dynamic signal lines.