Abstract: Integrated circuits may include memory interface circuitry operable to communicate with memory. The memory interface circuitry may include a memory controller and a memory interface circuit. The memory controller may fulfill memory access requests using the memory interface circuit. The memory controller may operate based on controller clock cycles of a controller clock, whereas the memory interface circuit may operate based on memory clock cycles of a memory clock. Each controller clock cycle may have a set of corresponding memory clock cycles. The memory interface circuitry may be configured using logic design computing equipment. The logic design computing equipment may identify memory timing requirements and controller latency requirements. The computing equipment may determine a command placement configuration that satisfies the timing and latency requirements. The computing equipment may configure the integrated circuit with the command placement configuration.

Abstract: Systems and methods for using memory commands are described. The systems include a memory controller. The memory controller receives a plurality of user transactions. The memory controller converts each user transaction into one or more row and column memory commands. The memory controller reorders the memory commands associated with the plurality of user transactions before sending the memory commands to a memory device.

Abstract: Systems and methods for using memory commands are described. The systems include a memory controller. The memory controller receives a plurality of user transactions. The memory controller converts each user transaction into one or more row and column memory commands. The memory controller reorders the memory commands associated with the plurality of user transactions before sending the memory commands to a memory device.