Abstract: Two or more circuits (e.g. processing cores of a graphics processor) operate synchronously at a fast clock frequency. A core interface to each of the processing cores is designed to communicate in synchronous fashion with one or more other core interfaces at a slow clock frequency. The fast clock is distributed to each processing core in a manner that provides minimized skew and jitter, e.g. with a balanced tree network. The slow clock is locally derived from the fast clock in each core interface. One of the core interfaces is selected to provide a synchronism signal, and the synchronism signal is distributed among the multiple core interfaces to synchronize the locally derived slow clocks.

Abstract: A method and a device for maintaining logic state stored in a storage device are described. For one embodiment, the device precharges at least two complimentary nodes in a storage device during the precharge cycle. During the evaluation cycle, the device receives an input data. After receipt of the input data, device stores at least one logic state at a storage node according to the input data. The device includes at least one conducting path to limit one store per each evaluation stage.