Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

Abstract: A CMP slurry composition which provides for a high Ge- or SiGe-to-dielectric material selectivity a low rate of Ge or SiGe recess formation includes an oxidant and a germanium removal rate enhancer including at least one of a methylpyridine compound and a methylpyridine derivative compound. In some examples, the slurry composition also includes an etching inhibitor. In some cases, the slurry composition may include an abrasive, a surfactant, an organic complexant, a chelating agent, an organic or inorganic acid, an organic or inorganic base, a corrosion inhibitor, or a buffer. The slurry composition may be distributed onto a surface of a polishing pad disposed on a platen that is configured to rotate. Additionally, a workpiece carrier configured to house a substrate may bring the substrate into contact with the rotating polishing pad and thereby polish the substrate utilizing the slurry composition.

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.

Abstract: A method includes forming a gate structure and an interlayer dielectric (ILD) layer over a substrate; selectively forming an inhibitor over the gate structure; performing an atomic layer deposition (ALD) process to form a dielectric layer over the ILD layer, wherein in the ALD process the dielectric layer has greater growing rate on the ILD than on the inhibitor; and performing an atomic layer etching (ALE) process to etch the dielectric layer until a top surface of the inhibitor is exposed, in which a portion of the dielectric layer remains on the ILD layer after the ALE process is complete.

Abstract: A method includes forming a bottom layer of a multi-layer mask over a first gate structure extending across a fin; performing a chemical treatment to treat an upper portion of the bottom layer of the multi-layer mask, while leaving a lower portion of the bottom layer of the multi-layer mask untreated; forming a sacrificial layer over the bottom layer of the multi-layer mask; performing a polish process on the sacrificial layer, in which the treated upper portion of the bottom layer of the multi-layer mask has a slower removal rate in the polish process than that of the untreated lower portion of the bottom layer of the multi-layer mask; forming middle and top layers of the multi-layer mask; patterning the multi-layer mask; and etching an exposed portion of the first gate structure to break the first gate structure into a plurality of second gate structures.

Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate. A first gate structure and a second gate structure are across the first and second fins, respectively. An insulating structure is formed between the first gate structure and the second gate structure and includes a first insulating layer separating the first fin from the second fin, a capping structure formed in the first insulating layer, and a second insulating layer covered by the first insulating layer and the capping structure.

Abstract: Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.

Abstract: A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Abstract: A semiconductor device includes a first vertical device having a first threshold and second vertical device having a second threshold. The first vertical device includes a first source; a first channel over the first source; a first drain over the first channel; a first conductive layer adjacent to the first channel; and a first gate adjacent to the first conductive layer. The second vertical device includes a second source; a second channel over the second source; a second drain over the second channel; a second conductive layer adjacent to the second channel; and a second gate adjacent to the second conductive layer.

Abstract: A chemical mechanical polishing (CMP) slurry composition includes an oxidant including oxygen, and an abrasive particle having a core structure encapsulated by a shell structure. The core structure includes a first compound and the shell structure includes a second compound different from the first compound, where a diameter of the core structure is greater than a thickness of the shell structure, and where the first compound is configured to react with the oxidant to form a reactive oxygen species.

Abstract: A method includes following steps. A semiconductor substrate is etched to form semiconductor fins. A dielectric material is deposited into a trench between the semiconductor fins. The semiconductor fins are etched such that top ends of the semiconductor fins are lower than a top surface of the dielectric material. After etching the semiconductor fins, epitaxially growing epitaxial fins on the semiconductor fins, respectively. A chemical mechanical polish (CMP) process is performed on the epitaxial fins, followed by cleaning the epitaxial fins using a non-contact-type cleaning device. The dielectric material is then such that the top surface of the dielectric material is lower than top ends of the epitaxial fins. A gate structure is formed across the epitaxial fins.

Abstract: A semiconductor device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, an inhibitor residue over gate structure and between the gate spacers, and source/drain structures on opposite sides of the gate structure. The inhibitor residue lines a sidewall of one of the gate spacers.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.

Abstract: A method of manufacturing an integrated circuit device is provided. A first feature, which has a first susceptibility to damage by chemical mechanical processing (CMP), is formed at a first height as measured from an upper surface of the substrate. A second feature, which has a second susceptibility to damage by the CMP, is formed at a second height as measured from the upper surface of the substrate and is laterally spaced from the first feature by a recess. The second height is greater than the first height, and the second susceptibility is less than the first susceptibility. A sacrificial coating is formed in the recess over an uppermost surface of the first feature. CMP is performed to remove a first portion of the sacrificial coating and expose an upper surface of the second feature while leaving a second portion of the sacrificial coating in place over the first feature.