Abstract: A display panel and a display device are provided. The display panel includes a regular display region and an irregular display region. The display panel also includes a first substrate and a second substrate that are disposed opposite to each other, a liquid crystal layer disposed between the first and second substrates, and a heating electrode layer stacked with the liquid crystal layer. In the irregular display region, the heating electrode layer includes a plurality of first heating wires, and each first heating wire is connected between a first electrode wire and a second electrode wire. At least one first heating wire serves as a target heating wire including a first sub-segment and a second sub-segment. The first sub-segment has a resistance per unit length smaller than the second sub-segment, and the first sub-segment is closer to the regular display region than the second sub-segment.

Abstract: Provided are a display panel and a display device. The display panel includes a display region and a non-display region. At least part of the non-display region is configured to be attached to a backlight module. The display panel also includes multiple heating wires located in the display region and the non-display region. In the same area, the resistance of heating wires located in the non-display region is higher than the resistance of heating wires located in the display region.

Abstract: Provided are a display panel and a spliced display device. The display panel includes pixel rows and spacing areas. The pixel rows include a type-A pixel row adjacent to a first panel edge and type-B pixel rows including a first type-B pixel row. The spacing areas correspond to and are adjacent to the type-B pixel rows, and close to the first panel edge. The pixel row includes light-emitting devices and pixel circuits. The pixel circuit includes a first part and a second part. In the type-A pixel row, the first part is located at a side of the light-emitting device close to the first panel edge, and the second part is located in the spacing area corresponding to the first type-B pixel row. In at least one type-B pixel row, the pixel circuit is located at a side of the light-emitting device close to the first panel edge.

Abstract: A display panel including a display area, subpixels located in the display area, and a shift register. The shift register includes a plurality of stages of shift units that is cascaded. Each of the plurality of stages of shift units is electrically connected to one of control signal lines and at least two of the subpixels respectively, and is configured to output a driving signal to the at least two of the subpixels in response to a control signal. The shift register is located in the display area, and at least one of the control signal lines is located in the display area.

Abstract: Provided are a display panel and a manufacturing method thereof. The display panel includes a base material and a first metal layer and a second metal layer which are laminated on the base material in a thickness direction of the display panel. The first metal layer includes first metal lines, the second metal layer includes second metal lines, the first metal lines extend in a first direction, and the second metal lines extend in a second direction, the first direction intersects the second direction. The first metal layer or the second metal layer includes third metal lines, a third metal line includes at least two first segments extending in the first direction and at least two second segments extending in the second direction, and two adjacent first segments are connected by one second segment. The display panel further includes a heating control assembly electrically connected to the third metal lines.

Abstract: Provided are a display panel and a spliced display device. The display panel includes pixel rows and spacing areas. The pixel rows include a type-A pixel row adjacent to a first panel edge and type-B pixel rows including a first type-B pixel row. The spacing areas correspond to and are adjacent to the type-B pixel rows, and close to the first panel edge. The pixel row includes light-emitting devices and pixel circuits. The pixel circuit includes a first part and a second part. In the type-A pixel row, the first part is located at a side of the light-emitting device close to the first panel edge, and the second part is located in the spacing area corresponding to the first type-B pixel row. In at least one type-B pixel row, the pixel circuit is located at a side of the light-emitting device close to the first panel edge.

Abstract: Provided are a display panel and a spliced display device. The display panel includes first and second edges, first and second pixel rows, and first spacing regions. The first pixel row is adjacent to the first edge and includes first sub-pixels and each including a first light-emitting device and a first pixel circuit. The second pixel row includes second sub-pixels and each including a second light-emitting device and a second pixel circuit. The first spacing region is located at a side of the second pixel row close to the first edge. The second pixel rows include a second A pixel row adjacent to the first pixel row. The first pixel circuit is located in the first spacing region corresponding to the second A pixel row, and the second pixel circuit is located at a side of the second light-emitting device close to the first edge.

Abstract: A display panel including a display region including first and second display regions, and sub-pixels in the display region, data lines electrically connected to the sub-pixels and including first data lines in the first display region and second data lines located in the second display region; a shift register in the first display region and including cascaded shift units, each shift unit being divided into at least two sub-units, and one sub-unit being located at a side of one sub-pixel connecting lines electrically connected to the sub-units of the shift units, one of the first data lines overlapping with one of the connecting lines in a direction perpendicular to a plane of the display panel; and compensation structures located in the second display region, and each overlapping with at least one of the second data lines in the direction.

Abstract: A gate drive circuit is disclosed. The gate drive circuit includes shift register units connected with gate lines. The gate drive circuit also includes clock signal lines to provide clock signals. A trigger signal terminal of the first shift register unit is connected with a first initial trigger signal line, and a trigger signal terminal of the p-th shift register unit is connected with an output terminal of the (p?1)-th shift register unit. An end signal terminal of the r-th shift register unit is connected with an output terminal of the (r+2M-1)-th shift register unit, low level signal terminals are connected with a first low level signal line, and reset signal terminals are connected with a reset signal line. In addition, forward scan signal terminals are connected with a first scan signal line, and backward scan signal terminals are connected with a second scan signal line.

Abstract: The present disclosure discloses a gate driver, an array substrate, a display panel and a display device so as to address problems in the gate driver that some shift register units become abnormal so that a succeeding shift register unit depending upon the shift register unit may not be triggered and consequently the entire GOA circuit may operate improperly and even become inoperative. The gate driver includes N shift register units, each of which is connected with respective one of N gate lines of a display panel, and a plurality of gate units. While a gate unit is enabled, the gate unit is configured to provide a current gate line with an output signal of a corresponding shift register unit connected to a preceding gate line and/or a corresponding shift register unit connected to a succeeding gate line.

Abstract: A gate drive circuit is disclosed. The gate drive circuit includes shift register units connected with gate lines. The gate drive circuit also includes clock signal lines to provide clock signals. A trigger signal terminal of the first shift register unit is connected with a first initial trigger signal line, and a trigger signal terminal of the p-th shift register unit is connected with an output terminal of the (p?1)-th shift register unit. An end signal terminal of the r-th shift register unit is connected with an output terminal of the (r+2M?1)-th shift register unit, low level signal terminals are connected with a first low level signal line, and reset signal terminals are connected with a reset signal line. In addition, forward scan signal terminals are connected with a first scan signal line, and backward scan signal terminals are connected with a second scan signal line.

Abstract: The present disclosure discloses a gate driver, an array substrate, a display panel and a display device so as to address problems in the gate driver that some shift register units become abnormal so that a succeeding shift register unit depending upon the shift register unit may not be triggered and consequently the entire GOA circuit may operate improperly and even become inoperative. The gate driver includes N shift register units, each of which is connected with respective one of N gate lines of a display panel, and a plurality of gate units. While a gate unit is enabled, the gate unit is configured to provide a current gate line with an output signal of a corresponding shift register unit connected to a preceding gate line and/or a corresponding shift register unit connected to a succeeding gate line.

Abstract: A display panel includes a first substrate including a first conducting wire disposed on an inner side of the first substrate, a second substrate disposed opposite to the first substrate, where a gate line and a first connecting terminal for transmitting a gate drive signal are disposed on a side of the second substrate facing the first substrate, the gate line includes a second connecting terminal at one end of the gate line; and a connecting layer disposed between the first substrate and the second substrate. The first connecting terminal and the second connecting terminal are electrically connected to two ends of the first conducting wire via the connecting layer respectively, and the second connecting terminal is electrically connected to the first connecting terminal via the first conducting wire, so the gate drive signal transmitted from the first connecting terminal is received by the gate line.

Abstract: A color filter substrate, a display panel and a display device are provided. The color filter substrate includes a first substrate, a black matrix layer located on the first substrate, and an electrostatic discharge wire layer located on the black matrix layer and connected to the black matrix layer. In the color filter substrate, the display panel and the display device, the electrostatic discharge wire layer is arranged on the black matrix layer of the color filter substrate. Hence, static electricity in the color filter substrate is discharged via the electrostatic discharge wire layer, and accordingly, the static electricity may not be accumulated in the color filter substrate, thereby improving the quality and performance of a display.

Abstract: A color filter substrate, a display panel and a display device are provided. The color filter substrate includes a first substrate, a black matrix layer located on the first substrate, and an electrostatic discharge wire layer located on the black matrix layer and connected to the black matrix layer. In the color filter substrate, the display panel and the display device, the electrostatic discharge wire layer is arranged on the black matrix layer of the color filter substrate. Hence, static electricity in the color filter substrate is discharged via the electrostatic discharge wire layer, and accordingly, the static electricity may not be accumulated in the color filter substrate, thereby improving the quality and performance of a display.

Abstract: A display panel includes a first substrate including a first conducting wire disposed on an inner side of the first substrate, a second substrate disposed opposite to the first substrate, where a gate line and a first connecting terminal for transmitting a gate drive signal are disposed on a side of the second substrate facing the first substrate, the gate line includes a second connecting terminal at one end of the gate line; and a connecting layer disposed between the first substrate and the second substrate. The first connecting terminal and the second connecting terminal are electrically connected to two ends of the first conducting wire via the connecting layer respectively, and the second connecting terminal is electrically connected to the first connecting terminal via the first conducting wire, so the gate drive signal transmitted from the first connecting terminal is received by the gate line.