Patents by Inventor Teodora Ossiander
Teodora Ossiander has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10157869Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.Type: GrantFiled: October 14, 2016Date of Patent: December 18, 2018Assignee: Intel CorporationInventors: Thorsten Meyer, Gerald Ofner, Teodora Ossiander, Frank Zudock, Christian Geissler
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Publication number: 20180150156Abstract: Some forms relate to wearable computing devices that include a “touch pad” like interface. In some forms, the example wearable computing devices may be integrated with (or attached to) textiles (i.e. clothing). In other forms, the example wearable computing devices may be attached directly to the skin of someone (i.e., similar to a bandage) that utilizes any of the example wearable computing devices. The example wearable computing devices include a flexible touch pad that may allow a user of the wearable computing device to more easily operate the wearable computing device. The example wearable computing devices described herein may include a variety of electronics. Some examples include a power supply and/or a communication device among other types of electronics.Type: ApplicationFiled: January 25, 2018Publication date: May 31, 2018Inventors: Sven Albers, Klaus Reingruber, Teodora Ossiander, Andreas Wolter, Sonja Koller, Georg Seidemann, Jan Proschwitz, Hans-Joachim Barth, Bastiaan Elshof
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Patent number: 9921694Abstract: Some forms relate to wearable computing devices that include a “touch pad” like interface. In some forms, the example wearable computing devices may be integrated with (or attached to) textiles (i.e. clothing). In other forms, the example wearable computing devices may be attached directly to the skin of someone (i.e., similar to a bandage) that utilizes any of the example wearable computing devices. The example wearable computing devices include a flexible touch pad that may allow a user of the wearable computing device to more easily operate the wearable computing device. The example wearable computing devices described herein may include a variety of electronics. Some examples include a power supply and/or a communication device among other types of electronics.Type: GrantFiled: December 16, 2014Date of Patent: March 20, 2018Assignee: Intel CorporationInventors: Sven Albers, Klaus Reingruber, Teodora Ossiander, Andreas Wolter, Sonja Koller, Georg Seidemann, Jan Proschwitz, Hans-Joachim Barth, Bastiaan Elshof
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Publication number: 20170103956Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.Type: ApplicationFiled: October 14, 2016Publication date: April 13, 2017Inventors: Thorsten Meyer, Gerald Ofner, Teodora Ossiander, Frank Zudock, Christian Geissler
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Patent number: 9601468Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.Type: GrantFiled: May 4, 2016Date of Patent: March 21, 2017Assignee: Intel CorporationInventors: Michael P. Skinner, Teodora Ossiander, Sven Albers, Georg Seidemann
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Patent number: 9472515Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.Type: GrantFiled: March 11, 2014Date of Patent: October 18, 2016Assignee: INTEL CORPORATIONInventors: Thorsten Meyer, Gerald Ofner, Teodora Ossiander, Frank Zudock, Christian Geissler
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Publication number: 20160247785Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.Type: ApplicationFiled: May 4, 2016Publication date: August 25, 2016Inventors: Michael P. Skinner, Teodora Ossiander, Sven Albers, Georg Seidemann
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Publication number: 20160224148Abstract: Some forms relate to wearable computing devices that include a “touch pad” like interface. In some forms, the example wearable computing devices may be integrated with (or attached to) textiles (i.e. clothing). In other forms, the example wearable computing devices may be attached directly to the skin of someone (i.e., similar to a bandage) that utilizes any of the example wearable computing devices. The example wearable computing devices include a flexible touch pad that may allow a user of the wearable computing device to more easily operate the wearable computing device. The example wearable computing devices described herein may include a variety of electronics. Some examples include a power supply and/or a communication device among other types of electronics.Type: ApplicationFiled: December 16, 2014Publication date: August 4, 2016Inventors: Sven ALBERS, Klaus Reingruber, Teodora Ossiander, Andreas Wolter, Sonja Koller, Georg Seidemann, Jan Proschwitz, Hans-Joachim Barth, Bastiaan Elshof
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Patent number: 9343389Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.Type: GrantFiled: August 14, 2015Date of Patent: May 17, 2016Assignee: Intel CorporationInventors: Michael P. Skinner, Teodora Ossiander, Sven Albers, Georg Seidemann
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Publication number: 20150357311Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.Type: ApplicationFiled: August 14, 2015Publication date: December 10, 2015Inventors: Michael P. Skinner, Teodora Ossiander, Sven Albers, Georg Seidemann
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Patent number: 9209143Abstract: An apparatus comprises a first integrated circuit (IC) die that includes a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, a second IC die including a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, wherein the second IC die is arranged adjacent to the first IC die, and includes an electrically conductive bond in contact with at least one of the top surface or the side surface of the multi-surface contact pad of the first IC die and the top surface of the multi-surface contact pad of the second IC die.Type: GrantFiled: September 26, 2013Date of Patent: December 8, 2015Assignee: Intel IP CorporationInventors: Georg Seidemann, Sven Albers, Teodora Ossiander, Michael Skinner, Hans-Joachim Barth, Harald Gossner, Reinhard Mahnkopf, Christian Mueller, Wolfgang Molzer
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Patent number: 9142475Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.Type: GrantFiled: August 13, 2013Date of Patent: September 22, 2015Assignee: Intel CorporationInventors: Michael P. Skinner, Teodora Ossiander, Sven Albers, Georg Seidemann
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Publication number: 20150262866Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 11, 2014Publication date: September 17, 2015Inventors: Thorsten Meyer, Gerald Ofner, Teodora Ossiander, Frank Zudock, Christian Geissler
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Publication number: 20150084202Abstract: An apparatus comprises a first integrated circuit (IC) die that includes a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, a second IC die including a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, wherein the second IC die is arranged adjacent to the first IC die, and includes an electrically conductive bond in contact with at least one of the top surface or the side surface of the multi-surface contact pad of the first IC die and the top surface of the multi-surface contact pad of the second IC die.Type: ApplicationFiled: September 26, 2013Publication date: March 26, 2015Inventors: Georg Seidemann, Sven Albers, Teodora Ossiander, Michael Skinner, Hans-Joachim Barth, Harald Gossner, Reinhard Mahnkoph, Christian Mueller, Wolfgang Molzer
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Publication number: 20150048520Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.Type: ApplicationFiled: August 13, 2013Publication date: February 19, 2015Inventors: Michael P. Skinner, Teodora Ossiander, Sven Albers, Georg Seidemann