Abstract: Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench.

Abstract: Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench.

Abstract: Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench.

Abstract: Disclosed is a circuit for preventing charging damage in an integrated circuit design, for example, a design having silicon over insulator (SOI) transistors. The circuit prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within the regions have electrically independent nets, identifying devices that may have a voltage differential between the source or drain, and gate as susceptible devices within a given region, and connecting an element across the source or drain, and the gate of each of the susceptible devices such that the element is positioned within the region. Alternatively, the method/circuit provides for connecting compensating conductors to an element to eliminate potential charging damage.

Abstract: A metal oxide semiconductor transistor having a slew-rate control is disclosed. The transistor having a slew-rate control includes an elongated diffusion area and an elongated gate overlying the diffusion area. The elongated diffusion area has at least two diffusion regions, each having a threshold voltage that is different from each other. The elongated gate has a gate contact at only one side of the elongated diffusion area.

Abstract: An SOI circuit configuration effective for minimizing plasma-induced charging damage during fabrication comprises the formation of charge collectors connected to the gate electrode and the semiconductor body, wherein each one of the charge collectors have the same or substantially the same shape and dimension. A connecting structure formed between a device fabricated on SOI substrate and substrate is delayed until the latter stages of processing.

Abstract: A metal oxide semiconductor transistor having a slew-rate control is disclosed. The transistor having a slew-rate control includes an elongated diffusion area and an elongated gate overlying the diffusion area. The elongated diffusion area has at least two diffusion regions, each having a threshold voltage that is different from each other. The elongated gate has a gate contact at only one side of the elongated diffusion area.

Abstract: Methods for fabricating a semiconductor structure is provided wherein the diffusion region includes at least two regions of different depth, the deepest of which is aligned to the trench isolation region of the structure. Semiconductor structures such as FETs, resistors, bipolar transistors, capacitors and diodes comprising a semiconductor substrate having a surface; an external device region on the surface of said semiconductor substrate; a channel region of a first dopant type in said semiconductor substrate under said FET; and a doped region of a second dopant type in said substrate, said doped region comprising a first portion abutting said channel region, of a first depth, and a second portion abutting said first portion, of a second depth which is deeper than the depth of the first portion is also provided.

Abstract: Circuits with SOI devices are coupled to a body bias voltage via a switch for selectively connecting the body bias voltage signals to the SOI device body. NMOS or PMOS SOI devices are used for the switched body SOI device and a FET is used for the switch and the gate terminal of the SOI device is connected to the FET device. The gate of the SOI device controls the FET switch connection of the body bias voltage signals to the SOI device to adjust the threshold value of the SOI device. Logic circuits incorporating the SOI devices are also disclosed, and the fabrication process for the SOI devices as well.