Abstract: A method and system in an information processing system are disclosed for efficiently maintaining copies of values stored within a plurality of registers. The information processing system includes first circuitry, second circuitry, and a plurality of buffers. The first circuitry processes an execution state of a first type of instruction which always specifies a destination of at least one of a first type of register or a second type of register, and which outputs first information in response thereto. The first circuitry also processes an execution stage of a second type of instruction which always specifies a destination of only a third type of register, and outputs second information in response thereto.

Abstract: A method and system in a data processing system of permitting concurrent processing of multiple conditional branch instructions are disclosed. A condition register is established within the processing system. First and second conditional branch instructions are dispatched during a single cycle of the processing system. Prior to speculatively executing the first conditional branch instruction, a first copy of the condition register is stored. Prior to speculatively executing the second conditional branch instruction, a second copy of the condition register is stored. Multiple copies of the condition register are concurrently maintained so that the first and second conditional branch instructions may be concurrently processed during a single cycle of the processing system.

Abstract: An approach for determining whether a current address is within an address range in which both the starting address of the range and the size of the address range are determined by variable register contents. Whereas the information in the variable register contents is in binary format, the current address is in a 2B format. The present invention provides logic for translating the binary formatted information so that it can be compared to the 2B formatted current address.

Abstract: A processor and method for speculatively executing a branch instruction are disclosed. The processor includes a branch prediction unit for predicting a resolution of a speculative branch instruction, which is selectively configurable such that resolution of the speculative branch instruction is predicted in response to only an address of the speculative branch instruction or in response to branch history of at least one previously executed branch instruction. The processor also includes an address calculation unit for determining a target address in response to the predicted resolution of the speculative branch instruction. In one embodiment, the processor further includes configuration logic for dynamically configuring the branch prediction logic.

Abstract: A method and system for an infinite precision split multiply and add operation which has increased speed. The method and system for providing a split multiply and add of a plurality of operands include a multiplier and an adder means. The multiplier multiplies a first portion of the plurality of operands, thereby providing a product. The adder, which combines the remaining operands and the product, comprise at least one pair of data paths. Each pair of data paths comprises a first data path and a second data path. The first data path comprises a first aligner, a first adder, and a first normalizer capable of shifting a mantissa by a substantially fewer number digits than the aligner. The second data path comprises a second aligner, a second adder, and a second normalizer capable of shifting a mantissa by a substantially larger number of digits than the aligner. Accordingly, the present invention includes split multiply and add data paths which, individually, are faster than a fused multiply and add.

Abstract: An apparatus and method to manage data flow dependencies so that a processor can complete instructions and write associated data to architected logical registers out of the program order. This increases the commission bandwidth of the processor allowing greater processor throughput, by allowing instructions to pass the completion stage prior to having produced data.

Abstract: A distributed completion control system for a microprocessor is disclosed. The system comprises a plurality of dispatch units, each of the dispatch units further comprises a dispatch queue responsive to a fetched address for receiving instructions; a plurality of control dependent tags; and means for indicating that the control dependent tags have been assigned to the appropriate instructions. The system further includes a plurality of execution units for receiving the instructions and the control dependent tags.

Abstract: A method and system for dynamically recovering a lookahead register-address-table (RAT) in a processor that executes program instructions. Each instruction that updates a logical register address is assigned to a different physical register address. Each of the instructions to be processed by the processor are stored in a fifo queue. The physical register address assignments for each of the instructions are stored in a first RAT, and information regarding instructions that have completed execution by the processor are stored in a second RAT. The method and system further comprises storing the physical register address assignments for non-branch instructions from the fifo queue in a recovery RAT. The first RAT is then restored after an interrupt occurs by copying the second RAT into the recovery RAT and then copying the recovery RAT into the first RAT.

Abstract: A method and system in a data processing system are disclosed for efficiently handling exceptions. The data processing system includes a register for storing indications of multiple instructions while the multiple instructions are being concurrently processed. An exception is generated within the data processing system. A determination is made whether the exception was generated by one of the multiple instructions. In response to a determination that one of the multiple instructions generated the exception, a determination is then made whether an indication of the instruction which generated the exception is stored in a particular position within a register within the data processing system. In response to a determination that the indication of the instruction is stored in the particular position within the register, the exception is associated with a first priority group.

Abstract: A method and system for reducing the dispatch latency of instructions of a processor provides for reordering the instructions in a predetermined format before the instructions enter the cache. The method and system also stores information in the cache relating to the reordering of the instructions. The reordered instructions are then provided to the appropriate execution units based upon the predetermined format. With this system, a dispatch buffer is not required when sending the instructions to the cache.

Abstract: A processor and method for speculatively executing an instruction loop are disclosed. In accordance with the method, the processor initiates execution of an instruction loop and counts each executed iteration of the instruction loop. Thereafter, an actual number of iterations that the instruction loop should be executed is determined. In response to the determination, a difference between the actual number of iterations that the instruction loop should be executed and the number of executed iterations is determined. In response to a determination that the difference is greater than zero, the instruction loop is executed an additional number of iterations equal to the difference. According to one embodiment, unexecuted fetched instructions within mispredicted iterations of the instruction loop are cancelled in response to a determination that the difference is less than zero. In addition, data results of mispredicted iterations of the instruction loop that have been executed are discarded.

Abstract: A method and system are provided for processing instruction threads. Execution is initiated by a processing system of a first set of instructions including a particular instruction. The particular instruction includes an indication of a second set of instructions. In response to execution of the particular instruction and to the processing system being of a first type, the processing system continues executing the first set while initiating execution of the second set. In response to execution of the particular instruction and to the processing system being of a second type, the processing system continues executing the first set without initiating execution of the second set.