Patents by Inventor Terrell Magee

Terrell Magee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory interleave for heterogeneous computing
    Patent number: 8443147
    Abstract: A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block accesses by certain compute elements and via non-cache-block accesses by certain other compute elements. The heterogeneous computing system may comprise one or more cache-block oriented compute elements and one or more non-cache-block oriented compute elements that share access to a common main memory. The cache-block oriented compute elements access the memory via cache-block accesses (e.g., 64 bytes, per access), while the non-cache-block oriented compute elements access memory via sub-cache-block accesses (e.g., 8 bytes, per access).
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: May 14, 2013
    Assignee: Convey Computer
    Inventors: Tony M. Brewer, Terrell Magee, J. Michael Andrewartha
  • MEMORY INTERLEAVE FOR HETEROGENEOUS COMPUTING
    Publication number: 20120079177
    Abstract: A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block accesses by certain compute elements and via non-cache-block accesses by certain other compute elements. The heterogeneous computing system may comprise one or more cache-block oriented compute elements and one or more non-cache-block oriented compute elements that share access to a common main memory. The cache-block oriented compute elements access the memory via cache-block accesses (e.g., 64 bytes, per access), while the non-cache-block oriented compute elements access memory via sub-cache-block accesses (e.g., 8 bytes, per access).
    Type: Application
    Filed: December 5, 2011
    Publication date: March 29, 2012
    Applicant: Convey Computer
    Inventors: Tony M. BREWER, Terrell MAGEE, J. Michael ANDREWARTHA
  • Memory interleave for heterogeneous computing
    Patent number: 8095735
    Abstract: A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block accesses by certain compute elements and via non-cache-block accesses by certain other compute elements. The heterogeneous computing system may comprise one or more cache-block oriented compute elements and one or more non-cache-block oriented compute elements that share access to a common main memory. The cache-block oriented compute elements access the memory via cache-block accesses (e.g., 64 bytes, per access), while the non-cache-block oriented compute elements access memory via sub-cache-block accesses (e.g., 8 bytes, per access).
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: January 10, 2012
    Assignee: Convey Computer
    Inventors: Tony M. Brewer, Terrell Magee, J. Michael Andrewartha
  • MEMORY INTERLEAVE FOR HETEROGENEOUS COMPUTING
    Publication number: 20100037024
    Abstract: A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block accesses by certain compute elements and via non-cache-block accesses by certain other compute elements. The heterogeneous computing system may comprise one or more cache-block oriented compute elements and one or more non-cache-block oriented compute elements that share access to a common main memory. The cache-block oriented compute elements access the memory via cache-block accesses (e.g., 64 bytes, per access), while the non-cache-block oriented compute elements access memory via sub-cache-block accesses (e.g., 8 bytes, per access).
    Type: Application
    Filed: August 5, 2008
    Publication date: February 11, 2010
    Applicant: Convey Computer
    Inventors: Tony M. Brewer, Terrell Magee, J. Michael Andrewartha