Patents by Inventor Terrence J. Tanis
Terrence J. Tanis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7697502Abstract: Multistage switching for mixed SONET VT traffic, such as VT1.5s and VT2s, is accomplished by employing an input time switch, a space switch and an output time switch. The input time switch and output time switch include VT1.5 time switches arranged to alter the time order of the input VT1.5s and VT2 time switches arranged to alter the time order to the input VT2s. The space switch includes a VT1.5 space switch arranged to order the input VT1.5s with respect to output channels in an output channel order different from the input channel order of the VT1.5s. The space switch also includes a VT2 space switch arranged to order the input VT2s with respect to output channels in an output channel order different from the input channel order of the VT2s.Type: GrantFiled: November 21, 2005Date of Patent: April 13, 2010Assignee: Tellabs Operations, Inc.Inventors: Thomas E. Ryan, Terrence J. Tanis
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Patent number: 7697445Abstract: A system and method for autonomous data path verification in a multi-module shelf configuration, such as in a digital cross-connect system, are disclosed. The system generally includes a source port module, a destination module, and optional n-stage network of mapping interface modules. The source port module is configured to reuse transport overhead bytes of received SONET or SDH signals by inserting data path verification data therefor. The destination module is configured to perform autonomous data path verification between the source port module and the destination module by examining the reused transport overhead bytes of the signals received from the source port module. The method generally includes reusing transport overhead bytes by inserting data path verification data into the overhead bytes of signals received by a first module, e.g., a source port module, and transmitting the signals with the data path verification data toward a second module, e.g., a destination port module.Type: GrantFiled: June 5, 2003Date of Patent: April 13, 2010Assignee: Tellabs Operations, Inc.Inventors: Brian L. Yarger, Satish K. Jena, Terrence J. Tanis, Robert Torstensson
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Publication number: 20080259963Abstract: A method for switching multi-rate communications is described. The method includes filling a first set of p timeslots with p sets of data from a first data collection of a first type, where the first data collection includes m sets of data and p is less than m. The method also includes loading at least one overflow timeslot with at least one overflow set of data from the first data collection, where the overflow set of data exceeds a size of the first set of p timeslots.Type: ApplicationFiled: June 25, 2008Publication date: October 23, 2008Applicant: TELLABS OPERATIONS, INC.Inventors: Terrence J. Tanis, Ravi Chandran, Daniel J. Marchok
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Patent number: 7411463Abstract: A method for measuring the damping factor of an Nth-order phase-locked loop, wherein N>1, and a system, apparatus, and program that operate in accordance with the method. The method includes applying a modulation source at an input to the phase-locked loop. The method also includes measuring the output response to various levels of frequency modulation, measuring the ?3 dB cutoff frequency of the phase-locked loop, and measuring the peak frequency of the phase-locked loop. The method further includes calculating the damping factor of the phase-locked loop as a function of the ?3 dB cutoff frequency and the peak frequency.Type: GrantFiled: October 31, 2006Date of Patent: August 12, 2008Assignee: Tellabs Operations, Inc.Inventor: Terrence J. Tanis
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Patent number: 7397827Abstract: A method for switching multi-rate communications is described. The method includes filling a first set of p timeslots with p sets of data from a first data collection of a first type, where the first data collection includes m sets of data and p is less than m. The method also includes loading at least one overflow timeslot with at least one overflow set of data from the first data collection, where the overflow set of data exceeds a size of the first set of p timeslots.Type: GrantFiled: December 11, 2003Date of Patent: July 8, 2008Assignee: Tellabs Operations, Inc.Inventors: Terrence J. Tanis, Ravi Chandran, Daniel J. Marchok
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Publication number: 20080111636Abstract: A method for measuring the damping factor of an Nth-order phase-locked loop, wherein N>1, and a system, apparatus, and program that operate in accordance with the method. The method includes applying a modulation source at an input to the phase-locked loop. The method also includes measuring the output response to various levels of frequency modulation, measuring the ?3 dB cutoff frequency of the phase-locked loop, and measuring the peak frequency of the phase-locked loop. The method further includes calculating the damping factor of the phase-locked loop as a function of the ?3 dB cutoff frequency and the peak frequency.Type: ApplicationFiled: October 31, 2006Publication date: May 15, 2008Applicant: TELLABS OPERATIONS, INC.Inventor: Terrence J. Tanis
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Patent number: 7027436Abstract: Multistage switching for mixed SONET VT traffic, such as VT1.5s and VT2s, is accomplished by employing an input time switch, a space switch and an output time switch. The input time switch and output time switch include VT1.5 time switches arranged to alter the time order of the input VT1.5s and VT2 time switches arranged to alter the time order to the input VT2s. The space switch includes a VT1.5 space switch arranged to order the input VT1.5s with respect to output channels in an output channel order different from the input channel order of the VT1.5s. The space switch also includes a VT2 space switch arranged to order the input VT2s with respect to output channels in an output channel order different from the input channel order of the VT2s.Type: GrantFiled: August 31, 2001Date of Patent: April 11, 2006Assignee: Tellabs Operations, Inc.Inventors: Thomas E. Ryan, Terrence J. Tanis
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Publication number: 20040246954Abstract: A system and method for autonomous data path verification in a multi-module shelf configuration, such as in a digital cross-connect system, are disclosed. The system generally includes a source port module, a destination module, and optional n-stage network of mapping interface modules. The source port module is configured to reuse transport overhead bytes of received SONET or SDH signals by inserting data path verification data therefor. The destination module is configured to perform autonomous data path verification between the source port module and the destination module by examining the reused transport overhead bytes of the signals received from the source port module. The method generally includes reusing transport overhead bytes by inserting data path verification data into the overhead bytes of signals received by a first module, e.g., a source port module, and transmitting the signals with the data path verification data toward a second module, e.g., a destination port module.Type: ApplicationFiled: June 5, 2003Publication date: December 9, 2004Applicant: Tellabs Operations, Inc.Inventors: Brian L. Yarger, Satish K. Jena, Terrence J. Tanis, Robert Torstensson
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Publication number: 20040120360Abstract: A method for switching multi-rate communications is described. The method includes filling a first set of p timeslots with p sets of data from a first data collection of a first type, where the first data collection includes m sets of data and p is less than m. The method also includes loading at least one overflow timeslot with at least one overflow set of data from the first data collection, where the overflow set of data exceeds a size of the first set of p timeslots.Type: ApplicationFiled: December 11, 2003Publication date: June 24, 2004Inventors: Terrence J. Tanis, Ravi Chandran, Daniel J. Marchok
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Patent number: 6628651Abstract: Input interfaces convert a predetermined data frame structure, such as a Sonet STS-1, into an internal format comprising a predetermined number of rows and columns, the rows being a multiple of a number evenly divisible into the bytes contained in the internal frame format. A time-space switch switches the frame format while storing a row of bytes in a data memory. Output interfaces convert the switched data to the same type of data frame format received at the input.Type: GrantFiled: April 3, 2000Date of Patent: September 30, 2003Assignee: Tellabs Operations, Inc.Inventors: Thomas E. Ryan, Terrence J. Tanis, Robert C. Klein, Daniel J. Marchok, Gary L. Davis
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Publication number: 20030048777Abstract: Multistage switching for mixed SONET VT traffic, such as VT1.5s and VT2s, is accomplished by employing an input time switch, a space switch and an output time switch. The input time switch and output time switch include VT1.5 time switches arranged to alter the time order of the input VT1.5s and VT2 time switches arranged to alter the time order to the input VT2s. The space switch includes a VT1.5 space switch arranged to order the input VT1.5s with respect to output channels in an output channel order different from the input channel order of the VT1.5s. The space switch also includes a VT2 space switch arranged to order the input VT2s with respect to output channels in an output channel order different from the input channel order of the VT2s.Type: ApplicationFiled: August 31, 2001Publication date: March 13, 2003Inventors: Thomas E. Ryan, Terrence J. Tanis