Patents by Inventor Terry C. Brown
Terry C. Brown has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8555137Abstract: A portable device (114) includes a power source (120), a volatile memory (118) requiring refreshing to avoid data loss, and a memory management module (116). The volatile memory (118) is operably coupled to the power source (120) for power. The memory management module (116) is operably coupled to the volatile memory (118). The memory management module (116) is also adapted to refresh the volatile memory (118) at a refresh rate which causes refresh-based errors and to correct the refresh-based errors. Also disclosed is a method for reduced power consumption by a volatile memory requiring refreshing to avoid data loss in which such a volatile memory is refreshed (122) at a refresh rate. All defective bits are detected (124) at the refresh rate. An error correction code is selected (126) for correcting the defective bits.Type: GrantFiled: October 23, 2007Date of Patent: October 8, 2013Assignee: Frankfurt GmbH, LLCInventor: Terry C. Brown
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Patent number: 8156778Abstract: The framer, also referred to as the scrambler/Reed-Solomon encoder (SRS), is a part of the transmitter and accepts user and control data in the form of one or more logical channels, partitions this data into frames, adds error correction codes, randomizes the data through a scrambler, and multiplexes logical channels into a single data stream. The multiplexed data is then passed to the constellation encoder as the next step in the formation of the VDSL symbol. The deframer, also referred as the descrambler/Reed-Solomon decoder (DRS), is part of the receiver and performs the inverse function of the framer.Type: GrantFiled: May 28, 2010Date of Patent: April 17, 2012Assignee: Metanoia Technologies, Inc.Inventors: Ravi G. Mantri, Christopher R. Hansen, Terry C. Brown
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Patent number: 8145696Abstract: A method for storage for complex numbers that employs a shared exponent field is disclosed. Rather than each floating point component of an complex number having its own distinct signed mantissa and exponent fields, each component includes a distinct signed mantissa field and shares an exponent field, thereby increasing the possible size of each distinct signed mantissa field by as much as one half the number of bits formerly employed to store a single distinct exponent field.Type: GrantFiled: March 26, 2009Date of Patent: March 27, 2012Assignee: Metanoia Technologies, Inc.Inventors: Christopher R. Hansen, Felician Bors, Terry C. Brown
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Patent number: 7804906Abstract: A multicarrier transceiver is disclosed that includes a digital signal processor with a plurality of memory locations, a direct memory, an encoder module coupled to receive data from the FIFO buffers, a decoder module coupled to receive data from the FIFO buffers, a Fourier transform module configured to perform an inverse Fast Fourier transform for transmit operations and to perform Fast Fourier transform (FFT) operations for receive operations, a plurality of distributed modules including the encoder module, the decoder module and the Fourier transform module, each module configured with a memory port, each memory port coupled to a peripheral bus and the DMA bus, a plurality of memory ports coupled to each of the distributed modules, the plurality of memory ports coupled to a peripheral bus, and a plurality of point-to-point buses coupled to each of the distributed modules, the point-to-point bus configured to enable data flow and testing and provide a bypass capability for each of the distributed modules.Type: GrantFiled: November 1, 2004Date of Patent: September 28, 2010Assignee: Metanoia Technologies, Inc.Inventors: Terry C. Brown, Christopher R. Hansen, Jeffrey C. Strait, Ravi G. Mantri, Felician Bors
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Patent number: 7729384Abstract: The framer, also referred to as the scrambler/Reed-Solomon encoder (SRS), is a part of the transmitter and accepts user and control data in the form of one or more logical channels, partitions this data into frames, adds error correction codes, randomizes the data through a scrambler, and multiplexes logical channels into a single data stream. The multiplexed data is then passed to the constellation encoder as the next step in the formation of the VDSL symbol. The deframer, also referred as the descrambler/Reed-Solomon decoder (DRS), is part of the receiver and performs the inverse function of the framer.Type: GrantFiled: November 1, 2005Date of Patent: June 1, 2010Assignee: Metanoia Technologies, Inc.Inventors: Ravi G. Mantri, Christopher R. Hansen, Terry C. Brown
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Publication number: 20090187616Abstract: A method for storage for complex numbers that employs a shared exponent field is disclosed. Rather than each floating point component of an complex number having its own distinct signed mantissa and exponent fields, each component includes a distinct signed mantissa field and shares an exponent field, thereby increasing the possible size of each distinct signed mantissa field by as much as one half the number of bits formerly employed to store a single distinct exponent field.Type: ApplicationFiled: March 26, 2009Publication date: July 23, 2009Applicant: Metanoia Technologies, Inc.Inventors: Christopher R. Hansen, Felician Bors, Terry C. Brown
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Patent number: 7529789Abstract: A method for storage for complex numbers that employs a shared exponent field is disclosed. Rather than each floating point component of an complex number having its own distinct signed mantissa and exponent fields, each component includes a distinct signed mantissa field and shares an exponent field, thereby increasing the possible size of each distinct signed mantissa field by as much as one half the number of bits formerly employed to store a single distinct exponent field.Type: GrantFiled: November 1, 2004Date of Patent: May 5, 2009Assignee: Metanoia Technologies, Inc.Inventors: Christopher R. Hansen, Felician Bors, Terry C. Brown
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Patent number: 7496618Abstract: A Fourier transform architecture and system for FFT and IFFT processing within multicarrier transceiver is disclosed that includes a programmable butterfly component, a memory and a programmable address generation unit. The architecture includes a butterfly component configured to perform a plurality of radix butterfly calculations, and a four bank memory configured to operate on sample data. The architecture further includes a programmable address generation unit coupled to the pipeline to enable the architecture to perform calculations independent of Fourier-based algorithms. A method for addressing memory banks for an FFT pipeline includes expressing an index in radix notation, computing a bank address for a bank memory, converting the bank address to a reduced size by ignoring one or more bits, and calculating the bank address within the reduced memory bank.Type: GrantFiled: November 1, 2004Date of Patent: February 24, 2009Assignee: Metanoia Technologies, Inc.Inventors: Terry C. Brown, Felician Bors
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Patent number: 7483319Abstract: A portable device (114) includes a power source (120), a volatile memory (118) requiring refreshing to avoid data loss, and a memory management module (116). The volatile memory (118) is operably coupled to the power source (120) for power. The memory management module (116) is operably coupled to the volatile memory (118). The memory management module (116) is also adapted to refresh the volatile memory (118) at a refresh rate which causes refresh-based errors and to correct the refresh-based errors. Also disclosed is a method for reduced power consumption by a volatile memory requiring refreshing to avoid data loss in which such a volatile memory is refreshed (122) at a refresh rate. All defective bits are detected (124) at the refresh rate. An error correction code is selected (126) for correcting the defective bits.Type: GrantFiled: May 27, 2008Date of Patent: January 27, 2009Inventor: Terry C. Brown
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Publication number: 20080253214Abstract: A portable electronic device is provided which comprises (a) a memory device (42) equipped with an interface clock which is controlled by a Delay Locked Loop (DLL) such that the memory device is configured to operate in a first mode characterized by a minimum clock rate CRmin; and (b) a controller (38) adapted to cause the memory device to operate in a second mode by disabling the DLL, wherein the second mode is characterized by a nonzero clock rate Rc<CRmin.Type: ApplicationFiled: April 5, 2007Publication date: October 16, 2008Applicant: Xware Technology, Inc.Inventors: Marc M. Stimak, Terry C. Brown, Daniel Benkman
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Publication number: 20080225614Abstract: A portable device (114) includes a power source (120), a volatile memory (118) requiring refreshing to avoid data loss, and a memory management module (116). The volatile memory (118) is operably coupled to the power source (120) for power. The memory management module (116) is operably coupled to the volatile memory (118). The memory management module (116) is also adapted to refresh the volatile memory (118) at a refresh rate which causes refresh-based errors and to correct the refresh-based errors. Also disclosed is a method for reduced power consumption by a volatile memory requiring refreshing to avoid data loss in which such a volatile memory is refreshed (122) at a refresh rate. All defective bits are detected (124) at the refresh rate. An error correction code is selected (126) for correcting the defective bits.Type: ApplicationFiled: May 27, 2008Publication date: September 18, 2008Applicant: FRANKFURT GMBH. LLCInventor: Terry C. Brown
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Patent number: 7379368Abstract: A portable device (114) includes a power source (120), a volatile memory (118) requiring refreshing to avoid data loss, and a memory management module (116). The volatile memory (118) is operably coupled to the power source (120) for power. The memory management module (116) is operably coupled to the volatile memory (118). The memory management module (116) is also adapted to refresh the volatile memory (118) at a refresh rate which causes refresh-based errors and to correct the refresh-based errors. Also disclosed is a method for reduced power consumption by a volatile memory requiring refreshing to avoid data loss in which such a volatile memory is refreshed (122) at a refresh rate. All defective bits are detected (124) at the refresh rate. An error correction code is selected (126) for correcting the defective bits.Type: GrantFiled: February 25, 2005Date of Patent: May 27, 2008Assignee: Frankfurt GmbH, LLCInventor: Terry C. Brown
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Patent number: 5627775Abstract: A random number generating apparatus includes a noise source, a circuit for generating timing signals from the noise source, and a digital circuit that freely and continuously cycles through a predetermined distribution of states. The states of the digital circuit are stored at random times in accordance with the timing signals and are collected to form bytes of random numbers.Type: GrantFiled: April 18, 1995Date of Patent: May 6, 1997Assignee: Applied Computing Systems, Inc.Inventors: Jung P. Hong, Terry C. Brown
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Patent number: RE43223Abstract: In a method, system and apparatus for management of dynamic memory in battery-powered devices, information is stored in dynamic memory, such as SDRAM chips. Chip partitioning minimizes the number of chips requiring power, minimum refresh rates reduce the power needed to maintain information, and a threshold for determining when to power down a battery powered device are used to maximize battery life.Type: GrantFiled: April 23, 2008Date of Patent: March 6, 2012Assignee: Frankfurt GmbH, LLCInventors: Marc Stimak, Terry C. Brown, Mike Minnick