Patents by Inventor Terry D. Little

Terry D. Little has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Analog signal verification using digital signatures
    Patent number: 7047173
    Abstract: A method for modeling analog signals that may comprise (A) detecting one or more attributed analog signals and (B) modeling the attributed analog signals by adding a signature to each of the one or more attributed analog signals.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: May 16, 2006
    Assignee: Cypress Semiconductor Corp.
    Inventors: Steven P. Larky, Terry D. Little
  • Linearized digital phase-locked loop
    Patent number: 6993105
    Abstract: A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal and a position of the first edge, (B) determining if the position is within a zone, (C) if the edge is not within the zone, adjusting the clock signal towards the position of the edge, (D) detecting a second edge of the data signal and a position of the second edge, (E) determining a in value indicating a position of the second edge, (F) adding the first value to a second value, wherein the second value indicates a position of a third edge of the data signal and (G) adjusting the clock signal based on the result of step (F).
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: January 31, 2006
    Assignee: Cypress Semiconductor Corp.
    Inventors: Terry D. Little, Bertrand J. Williams, Kamal Dalmia, Timothy D. Jordan
  • Linearized digital phase-locked loop method
    Patent number: 6950484
    Abstract: A method for synchronizing a clock signal to a data signal, comprising the steps of (A) detecting an edge of the data signal, (B) determining whether a position of the edge is within a zone and (B) if the edge is not within the zone, adjusting the clock signal towards the position of the edge.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: September 27, 2005
    Assignee: Cypress Semiconductor Corp.
    Inventors: Timothy D. Jordan, Terry D. Little, Kamal Dalmia
  • Linearized digital phase-locked loop
    Patent number: 6711226
    Abstract: A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal, (B) determining a first value indicating a position of the first edge, (C) adding the first value to a second value, wherein the second value indicates a position of a second edge of the data signal and (D) adjusting the clock signal, based on the result of step (C), if the result is greater than a predetermined value.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: March 23, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Bertrand J. Williams, Kamal Dalmia, Terry D. Little
  • Programmable latch that avoids a non-desired output state
    Patent number: 6549050
    Abstract: A circuit and method are provided for ensuring a non-desired output state of a latch or flip-flop cannot be produced. The latch can be configured as a set dominant, reset dominant, or memory dominant circuit by simply placing programmed voltage values on select transistors of the latch. The programmed values will cause either the set input, the reset input, or both set and reset inputs to have a complimentary effect on the output signals even though the set and reset inputs are at the same logic level. The set, reset, and memory dominant circuit is identical in structure; however, the set, reset, and memory dominant features are derived solely by placing programmed values on corresponding transistors within the identical structure. A generic latch circuit can, therefore, be said to operate in one of three dominant ways depending on the programmed values chosen by a selector and fed to a prioritizer.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: April 15, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: Steven C. Meyers, Terry D. Little
  • Linearized digital phase-locked loop
    Patent number: 6366145
    Abstract: An apparatus for synchronizing a clock signal to a data signal. The apparatus comprises a detector and a control circuit. The detector may be configured to produce a value representing a position of an edge of said data signal based upon a state of said clock signal. The control circuit may be configured to adjust the clock signal based upon the value.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: April 2, 2002
    Assignee: Cypress Semiconductor Corp.
    Inventors: Bertrand J. Williams, Kamal Dalmia, Terry D. Little, Timothy D. Jordan