Patents by Inventor Terry Fletcher

Terry Fletcher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9141466
    Abstract: Embodiments of systems, apparatuses, and methods for correcting double bit burst errors using a low density parity check technique are disclosed. In one embodiment, an apparatus includes an encoder to generate a parity vector by multiplying a first version of a data vector by a matrix. The parity vector is to identify correctable double-bit burst errors in a second version of the data vector. The apparatus also includes logic to concatenate the parity vector and the first version of the data vector.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: September 22, 2015
    Assignee: Intel Corporation
    Inventors: Andrew W. Martwick, Terry Fletcher
  • Patent number: 8402291
    Abstract: A method, device, and system are disclosed. In one embodiment the method includes causing a processor to enter into a first power state. Then an interrupt is received that signals the processor to leave the first power state. The method continues by causing the processor to remain in the first power state if the interrupt was received less than a minimum dwell time after the processor entered the first power state.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: March 19, 2013
    Assignee: Intel Corporation
    Inventor: Terry Fletcher
  • Patent number: 8392728
    Abstract: A method to reduce idle leakage power in I/O pins of an integrated circuit using external circuitry. Initially, I/O pins on a package are subdivided into those that will also remain powered up and those that will power down during idle state. When a system enters a low power mode, a signal is sent to the external circuitry. The signal notifies the I/O pins that always remain powered up to notify the external circuitry to power down the other set of I/O pins.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: March 5, 2013
    Assignee: Intel Corporation
    Inventors: Lance Hacking, Belliappa Kuttanna, Rajesh Patel, Ashish Choubal, Terry Fletcher, Steven S. Varnum, Binta Patel
  • Publication number: 20120084586
    Abstract: A method, device, and system are disclosed. In one embodiment the method includes causing a processor to enter into a first power state. Then an interrupt is received that signals the processor to leave the first power state. The method continues by causing the processor to remain in the first power state if the interrupt was received less than a minimum dwell time after the processor entered the first power state.
    Type: Application
    Filed: December 12, 2011
    Publication date: April 5, 2012
    Inventor: Terry Fletcher
  • Patent number: 8078891
    Abstract: A method, device, and system are disclosed. In one embodiment the method includes causing a processor to enter into a first power state. Then an interrupt is received that signals the processor to leave the first power state. The method continues by causing the processor to remain in the first power state if the interrupt was received less than a minimum dwell time after the processor entered the first power state.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: December 13, 2011
    Assignee: Intel Corporation
    Inventor: Terry Fletcher
  • Publication number: 20110161773
    Abstract: Embodiments of systems, apparatuses, and methods for correcting double bit burst errors using a low density parity check technique are disclosed. In one embodiment, an apparatus includes an encoder to generate a parity vector by multiplying a first version of a data vector by a matrix. The parity vector is to identify correctable double-bit burst errors in a second version of the data vector. The apparatus also includes logic to concatenate the parity vector and the first version of the data vector.
    Type: Application
    Filed: December 31, 2009
    Publication date: June 30, 2011
    Inventors: Andrew W. Martwick, Terry Fletcher
  • Publication number: 20090327553
    Abstract: A method, device, and system are disclosed. In one embodiment the method includes causing a processor to enter into a first power state. Then an interrupt is received that signals the processor to leave the first power state. The method continues by causing the processor to remain in the first power state if the interrupt was received less than a minimum dwell time after the processor entered the first power state.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Inventor: Terry Fletcher
  • Publication number: 20080155280
    Abstract: A method to reduce idle leakage power in I/O pins of an integrated circuit using external circuitry. Initially, I/O pins on a package are subdivided into those that will also remain powered up and those that will power down during idle state. When a system enters a low power mode, a signal is sent to the external circuitry. The signal notifies the I/O pins that always remain powered up to notify the external circuitry to power down the other set of I/O pins.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 26, 2008
    Inventors: Lance Hacking, Belliappa Kuttana, Rajesh Patel, Ashish Choubal, Terry Fletcher, Steven S. Varnum, Binta Patel
  • Publication number: 20070271060
    Abstract: In some embodiments, an apparatus comprises a thermal sensor to detect a first temperature reading at a location proximate a buffer circuit at a first point in time and to detect a second temperature reading at a location proximate a buffer circuit at a second point in time, logic to generate a buffer compensation activation signal when the second temperature reading differs from the first temperature reading by an amount exceeding a threshold, and logic to transmit the buffer compensation activation signal to a buffer compensation module. Other embodiments are described.
    Type: Application
    Filed: May 22, 2006
    Publication date: November 22, 2007
    Inventor: Terry Fletcher
  • Publication number: 20050068311
    Abstract: Systems and methods provide automatic switching of display update properties such as screen resolution, pixel depth, and refresh rate in response to a power management event. The display update property may be decreased when power is switched from AC power to DC power, for example, when the system is unplugged from a wall outlet and is running on battery power.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Inventors: Terry Fletcher, Edward Costales
  • Publication number: 20040111902
    Abstract: A pipe alignment device utilizing a light source to project a spot onto the opposite structure for use in spotting the locations of roof openings for plumbing ventilation pipes in new building construction. The device is in the form of a cylindrical housing having several different stepped diameters for insertion into top plate holes of different sizes. The different diameters are sized in accordance with various standard sized pipes and fittings. The light source may be integrated or insertable, and battery-operated or externally powered. One or more levels may also be included in the device to assist in the alignment process.
    Type: Application
    Filed: December 16, 2002
    Publication date: June 17, 2004
    Inventor: Terry Fletcher