Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A data processor for storing vector data in multiple locations within the processor using a pointer value and a mask value. In one embodiment, a multi-entry input data register is used to receive input data to be provided to a plurality of processing elements. A pointer value is used to address the multi-entry input data register. A mask value may be used to provide the same data to a plurality of locations within the input data register.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A data link controller is provided which is suitable for use in ISDN applications, employing bit-oriented protocols. The data link controller can be operated in a time-division multiplexed mode or a non-time-division multiplexed mode. In the multiplexed mode, data in one of up to thirty-one selectable time slots is received by the data link controller under control of a microprocessor. One of the time slots can be selected via the microprocessor which allows a lengthened contiguous number of bits to be received, effectively increasing the reception rate. In the non-multiplexed mode, data is received in a continuous stream. In the multiplexed mode, up to thirty-one time slots are available for transmission of data. One of the time slots can be selected which allows a lengthened continuous number of bits to be transmitted, effectively increasing the transmission rate. In the lengthened configuration, by doubling the length of the time slot, two 64 kbps B-channels can act as a single 128 kbps channel.

Abstract: A universal asynchronous receiver-transmitter (UART) (54) is dislosed which is compatible with an industry standard yet provides additional features. The UART can be selectably operated in a synchronous or an asynchronous mode. First-in, first-out (FIFO) registers (404,424) are provided for both the receiver and transmitter portions of the UART, and a parity error and special character recognizer unit (412) on the receive side flags characters when they are placed in the reveive FIFO. Reception of a special character or one with a parity error is reported to the user via an interrupt mechanism (430). A random access memory (RAM) (413) with the special character recognized stores user-supplied patterns which are recognized as special characters. User-accessible status and control registers (408) have bit positions which enable and control the enhanced functions of the UART while maintaining compatability with the industry standard.

Abstract: An integrated data protocol controller (IDPC)(10) is disclosed which includes on a single chip a data link controller (DLC)(52), a universal asynchronous receiver-transmitter (UART)(54) and a dual port timing controller (DPTC)(56). The IDPC is designed to support bit-oriented protocols such as is used in integrated services digital networks (ISDN). A microprocessor interface (50) on the IDPC chip permits a user to control and monitor the IDPC functions via a local microprocessor (18). The IDPC can be connected to a host processor (595) which shares a random access memory (RAM)(22a) with the local processor, allowing interprocessor communication via memory-resident buffers and mailboxes. A set of control and status registers is available within each of the main blocks of the IDPC--the DLC, the UART and the DPTC--to permit user access and control of the respective blocks. The DLC, the UART and the DPTC provide enhanced functions beyond those available in individual chips realizing a DLC, a UART or a DPTC.

Abstract: A data link controller (DLC) 52 is disclosed which employs buffers (100,106) on both receive and transmit sides. These last-in, first-out buffers contain a position indicating that a character is the last one of a packet. In this way, a user need not monitor reception or transmission on a character-by-character basis, but need only concern themselves with packets. The receive and transmit FIFO's generate requests for more characters by monitoring the number of characters stored and thereby automatically receive and transmit characters without processor intervention. A four-stage mechanism (600,602,604,606,608,610,612,614) permits monitoring of multiple contiguous frames (back-to-back frames) received. Control of the DLC is provided by status and control registers (112,212) which are accessible to the user via a microprocessor interface (50).