Abstract: A programmable logic array including a plurality of AND gates for providing product terms, a plurality of OR gates connected to receive the product terms for providing output signals, and circuitry for reducing power dissipation caused by the application of clock signals to the programmable logic array.

Abstract: The present invention discloses a semiconductor output circuit with temperature compensated noise control. The output circuit of the present invention presents an increase in speed, a reduction in power consumption, and a reduction in noise level as compared with the prior art temperature compensated noise control output circuits. These advantages are obtained by utilizing the present invention's current control means which current control means is driven by a temperature compensation circuit.

Abstract: An apparatus and method of increasing the speed of an input receiver circuit directly interfaces the wordlines of a memory array. The speed of the input receiver and wordline driver circuit is improved by means of an inverter and a look-ahead n-channel transistor coupled to the basic wordline driver buffer.

Abstract: The present invention discloses an improved two-stage macrocell for Programmable Logic Devices. According to the first stage of the improved circuit of the present invention's macrocell, combined NOR'ing, inverting, MUX'ing, and latching functions are performed by the single first stage. This single stage replaces the prior art multiple stages for performing the same NOR'ing, inverting, MUX'ing, and latching functions of the present invention. Since the present invention replaces the prior art multiple stages with a single stage, the speed of the present invention in performing the above NOR'ing, inverting, MUX'ing, and latching functions is significantly improved over the prior art. Furthermore, the present invention also discloses a second stage for a low-noise temperature-compensated output circuit.

Abstract: A dual loop phase locked loop system having a secondary loop for controlling various circuit, environmental and process variations. The secondary loop is comprised of a phase comparator, a filter, a transconductance amplifier and a one-shot, wherein the output of the one-shot is fed back as an input signal for comparison with a reference signal at the input of the phase comparator. The filter generates a correction voltage which is dependent on the phase difference determined by the phase comparator, and the transconductance amplifier generates a charging current corresponding to the error voltage from the filter, wherein the charging current controls the charging of the input capacitor to the one-shot circuit for determining the duration of the pulse width of the output of the one-shot. The one-shot based loop is inherently stable since there is only one pole near the origin of the S-Plane.

Abstract: An extended range logic circuit is activated to decrease the settling time and prevent slip, when phase difference of two signals being compared by a phase comparator reaches a slip point. The circuit provides error correction signals to compensate for the phase correction at a much faster rate when the phase error reaches a predetermined point, which is proximate to the slip point. However, the extended capture range circuit in only active during the lock acquisition. After lock is achieved the extended capture range logic is disabled, to provide better jitter performance.