Patents by Inventor Terry L. Sculley
Terry L. Sculley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8438036Abstract: In recent years, it has become commonplace for portable devices to generate analog audio signals from numerous sources, meaning that the codecs employed in these portable devices need to be able to utilize various digital bit streams at different sampling rates. To date, however, the circuitry for asynchronous sampling rate conversions for multiple bit streams has been complex, rigid, and power hungry. Here, a codec is provided which uses miniDSP cores to perform asynchronous sampling rate conversion efficiently and with reduced power consumption compared to other conventional codecs.Type: GrantFiled: September 3, 2009Date of Patent: May 7, 2013Assignee: Texas Instruments IncorporatedInventors: Shawn X. Yu, Terry L. Sculley
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Publication number: 20110054913Abstract: In recent years, it has become commonplace for portable devices to generate analog audio signals from numerous sources, meaning that the codecs employed in these portable devices need to be able to utilize various digital bit streams at different sampling rates. To date, however, the circuitry for asynchronous sampling rate conversions for multiple bit streams has been complex, rigid, and power hungry. Here, a codec is provided which uses miniDSP cores to perform asynchronous sampling rate conversion efficiently and with reduced power consumption compared to other conventional codecs.Type: ApplicationFiled: September 3, 2009Publication date: March 3, 2011Applicant: Texas Instruments IncorporatedInventors: Shawn X. Yu, Terry L. Sculley
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Publication number: 20100141310Abstract: A clock signal generator (1) includes a phase locked loop (PLL) circuit (25) which requires a reference clock signal of at least a predetermined first frequency (fDIGCLK). A first clock signal (REFCLK) of a second frequency (fREF) that is substantially lower than the first frequency (fDIGCLK) is multiplied so as to produce a second clock signal (DIGCLK) which has a frequency at least as high as the first frequency (fDIGCLK) and which is phase-locked with respect to the first clock signal (REFCLK). The second clock signal (DIGCLK) is applied to a reference signal input of the PLL circuit (25), which produces an output clock signal (PLLCLK or CLKOUT).Type: ApplicationFiled: December 8, 2008Publication date: June 10, 2010Inventors: Shawn Xianggang Yu, Terry L. Sculley
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Patent number: 7733151Abstract: A clock signal generator (1) includes a phase locked loop (PLL) circuit (25) which requires a reference clock signal of at least a predetermined first frequency (fDIGCLK). A first clock signal (REFCLK) of a second frequency (fREF) that is substantially lower than the first frequency (fDIGCLK) is multiplied so as to produce a second clock signal (DIGCLK) which has a frequency at least as high as the first frequency (fDIGCLK) and which is phase-locked with respect to the first clock signal (REFCLK). The second clock signal (DIGCLK) is applied to a reference signal input of the PLL circuit (25), which produces an output clock signal (PLLCLK or CLKOUT).Type: GrantFiled: December 8, 2008Date of Patent: June 8, 2010Assignee: Texas Instruments IncorporatedInventors: Shawn Xianggang Yu, Terry L. Sculley
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Patent number: 7479912Abstract: A low-power data conversion system for converting a serial digital data input signal (DIN) to an analog output signal (Vout) by generating the serial digital data input signal (DIN) at a first sample rate (fsin) in a burst mode, wherein the sampling frequency of the serial digital data input signal (DIN) has a predetermined ratio to the frequency of an external reference clock signal (SLEEPCLK or WCLK). The serial digital data input signal (DIN) is converted into parallel format. A FIFO system temporarily stores a predetermined number of samples (Din) of the parallel format digital data input signal. The samples (Din) have a first sample rate (fsin). The samples (Din) are converted to an analog output signal (Vout).Type: GrantFiled: September 13, 2007Date of Patent: January 20, 2009Assignee: Texas Instruments IncorporatedInventors: Shawn Xianggang, Mark S. Toth, Terry L. Sculley
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Patent number: 7408485Abstract: A sample rate converter suitable for use in an audio DAC includes a first estimating circuit (32A) generating first (TR) and second (STAMPR) signals synchronized to an asynchronous clock (MCLK) and representing the period and edge arrival times, respectively, of a reference clock (REFCLK). A second estimating circuit (32B) operates on the first and second signals to generate third (T1) and fourth (STAMP1) signals representing an input sample rate (32fsin) and arrival times of input data samples, respectively, which are applied to a coefficient and address generator (76) to generate read addresses and coefficients input to a FIFO memory (42) receiving digital input data at the input sample rate and a multiplication/accumulation circuit (78) receiving data from the FIFO memory. The multiplication/accumulation circuit produces an output signal (SRC-out) synchronized to the asynchronous clock at an output sample rate (32fsout).Type: GrantFiled: March 22, 2007Date of Patent: August 5, 2008Assignee: Texas Instruments IncorporatedInventors: Shawn Xianggang Yu, Terry L. Sculley
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Patent number: 7262716Abstract: An asynchronous sample rate converter interpolates and filters a digital audio input signal to produce a filtered, up-sampled first signal. A FIFO memory receives the first signal and stores samples thereof at locations determined by a write address and presents stored samples from locations determined by a read address. The presented samples are passed through an interpolation and resampling circuit to produce a continuous-time signal which is re-sampled to produce a signal that is up-sampled relative to a desired output. That signal then is filtered and down-sampled to produce the output signal. Sample rate estimating circuitry computes a difference signal representative of a time at which a data sample of the audio input signal is received and a time at which a corresponding audio output sample is required, and address generation circuitry generates the read and write addresses.Type: GrantFiled: December 20, 2002Date of Patent: August 28, 2007Assignee: Texas Instruments IncoporatedInventors: Xianggang Yu, Terry L. Sculley, Jung-Kuei Chang
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Publication number: 20040120361Abstract: An asynchronous sample rate converter interpolates and filters a digital audio input signal to produce a filtered, up-sampled first signal. A FIFO memory receives the first signal and stores samples thereof at locations determined by a write address and presents stored samples from locations determined by a read address. The presented samples are passed through an interpolation and resampling circuit to produce a continuous-time signal which is re-sampled to produce a signal that is up-sampled relative to a desired output. That signal then is filtered and down-sampled to produce the output signal. Sample rate estimating circuitry computes a difference signal representative of a time at which a data sample of the audio input signal is received and a time at which a corresponding audio output sample is required, and address generation circuitry generates the read and write addresses.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Xianggang Yu, Terry L. Sculley, Jung-Kuei Chang
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Patent number: 6747858Abstract: A digital sample rate converter converts a digital input signal (Din) having a first sample rate (Fs_in) to a corresponding digital output signal Dout having a second sample rate (Fs_out), wherein an upsampling circuit (3) upsamples the digital input signal (Din) by a factor of N and a feedback algorithm circuit (23A) receives a corresponding digital signal of the same sample rate (Fs_in*N) to produce a digital signal (X6) having a sample rate which is a second predetermined factor (M) times the second sample rate (Fs_out). That signal is filtered by a decimation filter (17) and then downsampled by a predetermined factor to produce the digital output signal (Dout) with the second sample rate (Fs_out).Type: GrantFiled: December 31, 2002Date of Patent: June 8, 2004Assignee: Texas Instruments IncorporatedInventors: Terry L. Sculley, Xianggang Yu
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Patent number: 6535154Abstract: Noise-shaped dynamic element matching in analog-to-digital and digital-to-analog converters is increased in such a way that the number of components increases linearly, rather than exponentially, as the number of bits is increased. A processor generates a plurality of input signals for a plurality of digital delta sigma modulators which, in turn, generate a plurality of control signals for selecting a plurality of weighted converter elements. The processor recursively generates the input signals in such a way that the control signals generated by some of the digital delta sigma modulators include error cancellation components to cancel error components in other control signals.Type: GrantFiled: November 5, 2001Date of Patent: March 18, 2003Assignee: Texas Instruments IncorporatedInventor: Terry L. Sculley
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Publication number: 20020169603Abstract: A method and apparatus for reducing noise in an output signal for particular application with an output signal of an analog-to-digital converter (“ADC”). An ADC is disclosed which includes processing circuitry to divide a signal into a plurality of frequency subbands and then evaluate the signal level in each of those frequency subbands. If the signal level in a particular frequency subband is below a predetermined noise threshold for a predetermined time interval, that frequency subband is muted until the signal level is outside of the threshold level. By “muting” the frequency subband in this way, a portion of the otherwise existing noise may be removed from the output signal.Type: ApplicationFiled: May 4, 2001Publication date: November 14, 2002Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Terry L. Sculley
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Patent number: 6326818Abstract: A method and apparatus for performing voltage-mode sample and hold functions while avoiding nonlinear charge injection. The method comprises oversampling an input signal and sampling an error signal, not the input signal directly, and through signal processing causing the error signal to be reduced to low amplitude. First order and higher order voltage-mode sample and hold circuitry embodiments are provided.Type: GrantFiled: March 16, 2000Date of Patent: December 4, 2001Assignee: ESS Technology, Inc.Inventor: Terry L. Sculley
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Patent number: 6147558Abstract: Two banks of differently-connected resistors are connected as an input to an op-amp feedback circuit.Type: GrantFiled: April 14, 1999Date of Patent: November 14, 2000Assignee: ESS Technology, Inc.Inventor: Terry L. Sculley