Abstract: The invention is a method for synchronizing the refresh cycles of a bank of self-refreshing interruptable DRAMs. The refresh cycles are synchronized through a bidirectional control path from each self-refreshing interruptable DRAM to its respective external refresh pin.

Abstract: The invention synchronizes the refresh cycles of a bank of self-refreshing DRAMs. The refresh cycles are synchronized through a bidirectional control path from each self-refreshing DRAM to its respective external refresh pin. An arbitration circuit determines the self-refreshing DRAM having a fastest timing sequence, maintains that timing sequence and shuts down all timing circuits having slower timing sequences. The arbitration circuit of each self-refreshing DRAM provides a refresh signal to each respective refresh circuit.

Abstract: The invention is a circuit synchronizing the refresh cycles of a bank of self-refreshing DRAMs. The refresh cycles are synchronized through a bidirectional control path from each self-refreshing DRAM to its respective external refresh pin. An arbitration circuit determines the self-refreshing DRAM having a fastest timing sequence, maintains that timing sequence and shuts down all timing circuits having slower timing sequences. The arbitration circuit of each self-refreshing DRAM provides a refresh signal to each respective refresh circuit.

Abstract: The invention is a circuit for synchronizing the refresh cycles of a bank of self-refreshing interruptable DRAMs. The refresh cycles are synchronized through a bidirectional control path from each self-refreshing interruptable DRAM to its respective external refresh pin.

Abstract: An external test mode enable signal (xTE) applied to a memory IC is filtered on board the memory IC to prevent inadvertent switching into test mode due to noise. In one approach, the test mode enable signal passes through an internal RC low-pass filter (18,20) to reject high frequency signals. Another approach is filtering the enable signal digitally using an xRAS* signal as a filter signal. Logic (FIG. 2) is provided to assert test mode (node C) only when the external enable signal has been asserted for at least a minimum time determined by the filter signal, again to avoid false switching. Either approach allows lowering test mode enable signal voltages below those used presently. The invention, therefore, can be used with particular advantage to maintain test mode enable noise margin in small geometry circuits which cannot withstand supervoltages.