Abstract: A semiconductor integrated circuit includes a power line and a power supply circuitry. The power supply circuitry includes: a first power supply circuit operating on a first power supply voltage and having an output connected with the power line; and a second power supply circuit operating on a second power supply voltage higher than the first power supply voltage and having an output connected with the power line. The first power supply circuit is configured to drive the power line to a first preset, voltage. The second power supply circuit is configured to drive the power line to a second preset voltage lower than the first preset voltage. The second power supply circuit is configured not to decrease a third power supply voltage generated on the power line when the third power supply voltage is higher than the second preset voltage.

Abstract: A power circuit section generates a first logic power supply voltage and an analog power supply voltage to supply to a first power supply line and a second power supply line, respectively. A regulator steps the first logic power supply voltage down to generate a second logic power supply voltage and supplies the second logic power supply voltage to a third power supply line. A logic circuit controls A source line driving section and A gate line driving section in response to a decrease of a voltage of the first power supply line so that the charge stored in the display panel is discharged. A charge transporting path is configured to transport the charge from the second power supply line to a third power supply line in response to the decrease of the voltage of the first power supply line.

Abstract: A power circuit section generates a first logic power supply voltage and an analog power supply voltage to supply to a first power supply line and a second power supply line, respectively. A regulator steps the first logic power supply voltage down to generate a second logic power supply voltage and supplies the second logic power supply voltage to a third power supply line. A logic circuit controls A source line driving section and A gate line driving section in response to a decrease of a voltage of the first power supply line so that the charge stored in the display panel is discharged. A charge transporting path is configured to transport the charge from the second power supply line to a third power supply line in response to the decrease of the voltage of the first power supply line.

Abstract: A semiconductor integrated circuit includes a power line and a power supply circuitry. The power supply circuitry includes; a first power supply circuit operating on a first power supply voltage and having an output connected with the power line; and a second power supply circuit operating on a second power supply voltage higher than the first power supply voltage and having an output connected with the power line. The first power supply circuit is configured to drive the power line to a first preset, voltage. The second power supply circuit is configured to drive the power line to a second preset voltage lower than the first preset voltage. The second power supply circuit is configured not to decrease a third power supply voltage generated on the power line when the third power supply voltage is higher than the second preset voltage.

Abstract: A drive circuit which outputs an output signal to an output terminal, includes a drive transistor configured to output a gradation current to the output terminal; a single differential amplifier; a resistance element connected with the drive transistor; and a plurality of switches. The plurality of switches are controlled such that a precharge voltage is outputted from the differential amplifier to the output terminal in a first period while blocking off an output from the drive transistor and such that a gradation current is outputted from the drive transistor to the output terminal in a second period after the first period.

Abstract: A display data receiving circuit of the present invention includes a PLL circuit 25 which generates internal clock signal ICLK having an integral multiple of the frequency of differential clock signals CLK and /CLK in response to differential clock signals CLK and /CLK, and a serial/parallel conversion circuit 23 which receives serial data signal transmitting display data in synchronization with the internal clock signal ICLK, and generates parallel data signal by executing serial/parallel conversion for the serial data signal. The serial/parallel conversion circuit 23 is configured to be able to execute either a single edge operation, which receives serial data signals in response to one of a rising edge and a falling edge of the internal clock signal ICLK, or a double edge operation, which receives serial data signals in response to both of a rising edge and a falling edge of the internal clock signal ICLK.

Abstract: A display device uses a plurality of pixel circuits each of which includes a light-emitting element; a light-emission control switching element; a current control circuit for supplying a driving current, which corresponds to gray-level display data, to the light-emitting element via the light-emission control switching element; and a voltage control circuit, which includes a first capacitance element for storing a voltage corresponding to the gray-level display data, and controls ON/OFF operation of the light-emission switching element in accordance with the voltage stored. If the gray-level display data is data for causing the light-emitting element to display less than a certain luminance, the current control circuit supplies the light-emitting element with a constant driving current corresponding to the gray-level display data for displaying the certain luminance, and the voltage control circuit controls the ON time of the light-emission control switching element in accordance with a voltage stored.

Abstract: A drive circuit for a display apparatus includes a gradation voltage generation circuit and a D/A conversion circuit. The gradation voltage generation circuit generates a plurality of different first gradation voltages and a plurality of different second gradation voltages. The D/A conversion circuit drives a light emitting element of a pixel through a data line with a gradation voltage based on one of the first gradation voltages as a first specific gradation voltage in a precharge period and drives the light emitting element of the pixel through the data line with a gradation current based on one of the second gradation voltages as a second specific gradation voltage. The D/A conversion circuit includes a voltage driver to drive the light emitting element, and a current driver to drive the light emitting element.

Abstract: Disclosed is a display driver that includes a first current driver circuit, a second current driver circuit and a reference current source circuit. The first current driver circuit, which has plural current sources the output current values of which are determined based on a reference current, and switch circuits for on/off controlling the current path between the plural current sources and the current output terminal based on video signal composed of plural bits. The first current driver circuit outputs a first output current conforming to the video signal. The second current driver circuit outputs the second output current conforming to the video signal, while the reference current source circuit variably controls the reference current based on the value of the video signal. A current that is the result of combining the first and second output currents from the first and second current driver circuits is output as an output current.

Abstract: A current drive circuit is provided with a bias generator and a current output unit; wherein the bias generator is provided with: p-channel MOS transistor, p-channel MOS transistor, and reference current source; and the current output unit is provided with: p-channel MOS transistor, switch means, p-channel MOS transistor, and output terminal.

Abstract: A display data receiving circuit of the present invention includes a PLL circuit 25 which generates internal clock signal ICLK having an integral multiple of the frequency of differential clock signals CLK and /CLK in response to differential clock signals CLK and /CLK, and a serial/parallel conversion circuit 23 which receives serial data signal transmitting display data as in synchronization with the internal clock signal ICLK, and generates parallel data signal by executing serial/parallel conversion for the serial data signal. The serial/parallel conversion circuit 23 is configured to be able to both of a single edge operation which receives serial data signals in response to one of a rising edge and a falling edge of the internal clock signal ICLK, and a double edge operation which receives serial data signals in response to both of a rising edge and a falling edge of the internal clock signal ICLK.

Abstract: A drive circuit which outputs an output signal to an output terminal, includes a drive transistor configured to output a gradation current to the output terminal; a single differential amplifier; a resistance element connected with the drive transistor; and a plurality of switches. The plurality of switches are controlled such that a precharge voltage is outputted from the differential amplifier to the output terminal in a first period while blocking off an output from the drive transistor and such that a gradation current is outputted from the drive transistor to the output terminal in a second period after the first period.

Abstract: A sample-and-hold circuit according to the present invention includes an amplifier circuit amplifying a signal from an input terminal to output the amplified signal to an output terminal, a first switch connected to the input terminal, and a second switch arranged in parallel to the first switch and connected to the input terminal. Hence, an amplifier circuit operable at high speeds can be provided. In addition, a driver circuit for applying a grayscale voltage to each signal line of a display device includes a grayscale voltage output unit outputting a grayscale voltage, a precharge voltage generating unit generating a precharge voltage for a predetermined period before scanning, at a time of displaying on the display device, and an amplifier circuit amplifying an input signal to output the amplified signal to the display device.

Abstract: A drive circuit for a display apparatus includes a gradation voltage generation circuit and a D/A conversion circuit. The gradation voltage generation circuit generates a plurality of different first gradation voltages and a plurality of different second gradation voltages. The D/A conversion circuit drives a light emitting element of a pixel through a data line with a gradation voltage based on one of the first gradation voltages as a first specific gradation voltage in a precharge period and drives the light emitting element of the pixel through the data line with a gradation current based on one of the second gradation voltages as a second specific gradation voltage. The D/A conversion circuit includes a voltage driver to drive the light emitting element, and a current driver to drive the light emitting element.

Abstract: Disclosed is a display driver that includes a first current driver circuit, a second current driver circuit and a reference current source circuit. The first current driver circuit, which has plural current sources the output current values of which are determined based on a reference current, and switch circuits for on/off controlling the current path between the plural current sources and the current output terminal based on video signal composed of plural bits. The first current driver circuit outputs a first output current conforming to the video signal. The second current driver circuit outputs the second output current conforming to the video signal, while the reference current source circuit variably controls the reference current based on the value of the video signal. A current that is the result of combining the first and second output currents from the first and second current driver circuits is output as an output current.

Abstract: Disclosed is a display driver that includes a first current driver circuit, which has a plurality of current sources for outputting current of a value decided based upon a reference current, and switch circuits that on/off control current paths between the plurality of current sources and a current output terminal based upon a prescribed lower-order bit signal of a video signal, for outputting a first output current conforming to the prescribed lower-order bit signal of the video signal; a second current driver circuit for outputting a second output current conforming to a higher-order bit signal of the video signal; and a current-source circuit for varying the reference current based upon the higher-order bit signal of the video signal. A current that is the result of combining the first and second output currents from the first and second current driver circuits is output as an output current.

Abstract: A current drive circuit is provided with a bias generator and a current output unit; wherein the bias generator is provided with: p-channel MOS transistor, p-channel MOS transistor, and reference current source; and the current output unit is provided with: p-channel MOS transistor, switch means, p-channel MOS transistor, and output terminal.