Patents by Inventor Teruhiko Amano
Teruhiko Amano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9620214Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: GrantFiled: April 20, 2015Date of Patent: April 11, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
-
Publication number: 20150228341Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: ApplicationFiled: April 20, 2015Publication date: August 13, 2015Inventors: Naoya WATANABE, Isamu HAYASHI, Teruhiko AMANO, Fukashi MORISHITA, Kenji YOSHINAGA, Mihoko AKIYAMA, Shinya MIYAZAKI, Masakazu ISHIBASHI, Katsumi DOSAKA
-
Patent number: 9042148Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: GrantFiled: January 9, 2014Date of Patent: May 26, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
-
Publication number: 20140126264Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: ApplicationFiled: January 9, 2014Publication date: May 8, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Naoya WATANABE, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
-
Patent number: 8638583Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: GrantFiled: September 15, 2012Date of Patent: January 28, 2014Assignee: Renesas Electronics CorporationInventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
-
Publication number: 20130010513Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: ApplicationFiled: September 15, 2012Publication date: January 10, 2013Inventors: Naoya WATANABE, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
-
Patent number: 8310852Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: GrantFiled: March 13, 2012Date of Patent: November 13, 2012Assignee: Renesas Electronics CorporationInventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
-
Publication number: 20120170344Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: ApplicationFiled: March 13, 2012Publication date: July 5, 2012Applicant: Renesas Electronics CorporationInventors: Naoya WATANABE, Isamu HAYASHI, Teruhiko AMANO, Fukashi MORISHITA, Kenji YOSHINAGA, Mihoko AKIYAMA, Shinya MIYAZAKI, Masakazu ISHIBASHI, Katsumi DOSAKA
-
Patent number: 8164934Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: GrantFiled: March 9, 2010Date of Patent: April 24, 2012Assignee: Renesas Electronics CorporationInventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
-
Publication number: 20100165691Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: ApplicationFiled: March 9, 2010Publication date: July 1, 2010Applicant: Renesas Technology Corp.Inventors: Naoya WATANABE, Isamu HAYASHI, Teruhiko AMANO, Fukashi MORISHITA, Kenji YOSHINAGA, Mihoko AKIYAMA, Shinya MIYAZAKI, Masakazu ISHIBASHI, Katsumi DOSAKA
-
Publication number: 20070247885Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: ApplicationFiled: April 5, 2007Publication date: October 25, 2007Inventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
-
Patent number: 6756652Abstract: In a dummy word line region, a second metal interconnection line is arranged, and a connection between a low-resistive metal interconnection line constituting a word line arranged in a normal word line region and a lower gate electrode line is shifted. In a bit line twisting region, a memory cell gate electrode line is arranged to interconnect the gates of access transistors of memory cells, and a twisted bit line structure is implemented utilizing an upper metal interconnection line. A memory cell array region can more efficiently be used.Type: GrantFiled: June 6, 2003Date of Patent: June 29, 2004Assignee: Renesas Technology Corp.Inventors: Kenji Yano, Teruhiko Amano
-
Publication number: 20040089913Abstract: In a dummy word line region, a second metal interconnection line is arranged, and a connection between a low-resistive metal interconnection line constituting a word line arranged in a normal word line region and a lower gate electrode line is shifted. In a bit line twisting region, a memory cell gate electrode line is arranged to interconnect the gates of access transistors of memory cells, and a twisted bit line structure is implemented utilizing an upper metal interconnection line. A memory cell array region can more efficiently be used.Type: ApplicationFiled: June 6, 2003Publication date: May 13, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Kenji Yano, Teruhiko Amano
-
Patent number: 6462999Abstract: In the configuration of a charge confinement type sense amplifier, activation/inactivation of a charge containing gate and activation/inactivation of a sense amplifier circuit are controlled by different control signals. Thus, a layout area of the sense amplifier for reading of internal data is reduced.Type: GrantFiled: July 18, 2001Date of Patent: October 8, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Teruhiko Amano
-
Publication number: 20020118584Abstract: A row including a defective memory cell is replaced by a row of redundant memory cell, independently in each of a pair of memory blocks on opposing sides of a pair of row decoders 11. A redundancy determining circuit 1 for performing the replacement is provided for each memory block, and in the redundancy determining circuit 1, a plurality of fuse boxes 2 are arranged. Accordingly, as the fuses are laid-out in efficient manner, a semiconductor memory device is provided in which the circuits can be effectively arranged on the chip.Type: ApplicationFiled: April 30, 2002Publication date: August 29, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Teruhiko Amano
-
Patent number: 6411556Abstract: A row including a defective memory cell is replaced by a row of redundant memory cell, independently in each of a pair of memory blocks on opposing sides of a pair of row decoders 11. A redundancy determining circuit 1 for performing the replacement is provided for each memory block, and in the redundancy determining circuit 1, a plurality of fuse boxes 2 are arranged. Accordingly, as the fuses are laid-out in efficient manner, a semiconductor memory device is provided in which the circuits can be effectively arranged on the chip.Type: GrantFiled: September 22, 2000Date of Patent: June 25, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Teruhiko Amano
-
Publication number: 20020075731Abstract: In the configuration of a charge confinement type sense amplifier, activation/inactivation of a charge containing gate and activation/inactivation of a sense amplifier circuit are controlled by different control signals. Thus, a layout area of the sense amplifier for reading of internal data is reduced.Type: ApplicationFiled: July 18, 2001Publication date: June 20, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Teruhiko Amano
-
Patent number: 6337506Abstract: A power supply circuit and an oscillation circuit or the like of noise generation sources are concentrated, and the periphery thereof is surrounded by a guard ring. Guard ring is provided to have bonding pads at least partially thereon. Guard ring is effectively provided utilizing the region below bonding pads, so that effective noise reduction is achieved while preventing increase in chip area.Type: GrantFiled: July 16, 1998Date of Patent: January 8, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Fukashi Morishita, Teruhiko Amano, Kazutami Arimoto, Tetsushi Tanizaki, Takeshi Fujino, Takahiro Tsuruda, Mitsuya Kinoshita, Mako Kobayashi
-
Publication number: 20010045583Abstract: A power supply circuit and an oscillation circuit or the like of noise generation sources are concentrated, and the periphery thereof is surrounded by a guard ring. Guard ring is provided to have bonding pads at least partially thereon. Guard ring is effectively provided utilizing the region below bonding pads, so that effective noise reduction is achieved while preventing increase in chip area.Type: ApplicationFiled: July 16, 1998Publication date: November 29, 2001Inventors: FUKASHI MORISHITA, TERUHIKO AMANO, KAZUTAMI ARIMOTO, TETSUSHI TANIZAKI, TAKESHI FUJINO, TAKAHIRO TSURUDA, MITSUYA KINOSHITA, MAKO KOBAYASHI
-
Patent number: 6272034Abstract: A control circuit portion which controls the operations of memory cells is concentrated in a central portion and heat radiation plates are placed thereon via adhesive. A semiconductor integrated circuit having a function of the MPU or the like is placed above the control circuit portion via a bump electrode. The control circuit portion and a memory block are formed on separate chips respectively.Type: GrantFiled: June 29, 2000Date of Patent: August 7, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Mitsuya Kinoshita, Fukashi Morishita, Kazutami Arimoto, Takeshi Fujino, Tetsushi Tanizaki, Takahiro Tsuruda, Teruhiko Amano, Mako Kobayashi