Abstract: A control device configured to control a storage device includes a memory and a processor coupled to the memory and configured to store, into the storage device, a plurality of data blocks including a plurality of data patterns, classify the plurality of data blocks into the plurality of data patterns, for each of the plurality of data patterns, count numbers of the classified plurality of data blocks classified into each of the plurality of data patterns, read a first data block among the plurality of data blocks from the storage device, select a first data pattern from the plurality of data patterns based on the counted numbers when an error is detected in first data included in the first data block, replacing the first data included in the first data block with the selected first data pattern, and output the first data block including the first data pattern.

Abstract: A control device configured to control a storage device includes a memory and a processor coupled to the memory and configured to store, into the storage device, a plurality of data blocks including a plurality of data patterns, classify the plurality of data blocks into the plurality of data patterns, for each of the plurality of data patterns, count numbers of the classified plurality of data blocks classified into each of the plurality of data patterns, read a first data block among the plurality of data blocks from the storage device, select a first data pattern from the plurality of data patterns based on the counted numbers when an error is detected in first data included in the first data block, replacing the first data included in the first data block with the selected first data pattern, and output the first data block including the first data pattern.

Abstract: A control apparatus that causes data in a first storage unit to be written in a second storage unit, with power supplied from a sub power supply, when supply of power from a main power supply is discontinued, the control apparatus includes a remaining feed duration obtaining unit that obtains remaining feed duration during which the sub power supply can supply the power; and a retry count setting unit that sets a maximum retry count for writing the data from the first storage unit to the second storage unit, based on the remaining feed duration obtained by the remaining feed duration obtaining unit, when an error occurs while the data is being written.

Abstract: A storage device includes a controller device and a memory device. The controller device transmits communication information to which route information is added, the route information indicating a route to a destination of the communication information and including an address of a relay point that the communication information passes through before reaching the destination of the communication information. The memory device receives the communication information, and to transmit the communication information to a next relay point, when the destination of the communication information is not the local memory device, by using the address of the relay point included in the route information of the communication information.

Abstract: An information processing device includes: a processor; a first storage device configured to hold data that is read and written by the processor; and a controller configured to control data transfer between the processor and the first storage device, wherein the controller: reads out first data from the first storage device through a path without a data protection function; generates error check information for checking an error of the first data; writes the error check information as first error check information in a storage area bypassing the path; writes the error check information as second error check information in the first storage device through the path; compares the first error check information and the second error check information to each other; and determines, when the first error check information and the second error check information do not match each other, that an error has occurred in the path.

Abstract: A data converting method includes counting for each bit pattern among bit patterns that a data segment of a specific number of bits can assume, the number of data segments that have the bit pattern, where the data segments are segments of write_data written to a storage medium storing two types of bit values among which a first value has a higher error occurrence rate than a second value; correlating a bit pattern selected as a conversion source pattern, from among the bit patterns in descending order of count results, with a bit pattern selected as a conversion target pattern, from among the bit patterns in descending order of quantities of the second value respectively included in the bit patterns; and converting for each conversion source bit pattern, data segments having the conversion source bit pattern, into converted data segments having the correlated conversion target bit pattern.

Abstract: A recording and reproducing device includes a plurality of data storing units, a control unit, a first error detection-and-correction unit, and a second error detection-and-correction unit. The control unit creates stripe data with a predetermined write capacity, creates a redundant group, associates a plurality of pieces of stripe data, and controls the writing of the associated data into each of the plurality of the data storing units. The first error detection-and-correction unit detects whether an error is present in each of the pieces of the stripe data, and corrects the stripe data. The second error detection-and-correction unit groups the second error correction code and the pieces of the stripe data, creates a plurality of error correction groups, detects whether an error is present in each of the pieces of the split stripe data in the same error correction group, and corrects the split stripe data.

Abstract: A write DMA includes a write unit, a read unit and a parity generation unit. The read unit reads parity data from one of two NAND flashes storing the parity data therein. The parity generation unit generates parity data based on the read parity data and a plurality of stripes obtained by dividing user data. The write unit writes a stripe into any of a plurality of NAND flashes storing stripes therein, and writes generated parity data into the other NAND flash from which parity data is not read.

Abstract: A control apparatus that causes data in a first storage unit to be written in a second storage unit, with power supplied from a sub power supply, when supply of power from a main power supply is discontinued, the control apparatus includes a remaining feed duration obtaining unit that obtains remaining feed duration during which the sub power supply can supply the power; and a retry count setting unit that sets a maximum retry count for writing the data from the first storage unit to the second storage unit, based on the remaining feed duration obtained by the remaining feed duration obtaining unit, when an error occurs while the data is being written.

Abstract: A control apparatus includes a capacitor to store electric power supplied from the power supply unit and to supply the stored electric power to the control apparatus when the power supply from the power supply unit is stopped, a first nonvolatile memory, a second nonvolatile memory, a first controller, and a second controller. The first controller writes the data, stored in the cache memory, into the first nonvolatile memory when the external power supply is stopped verifies whether the data stored in the first nonvolatile memory is normal, and sends information of area where the data in the first nonvolatile memory is not normal when the verification indicates that the writing is not normal. And the second controller writes the information sent from the first controller into the second nonvolatile memory.

Abstract: A storage device includes a controller device and a memory device. The controller device transmits communication information to which route information is added, the route information indicating a route to a destination of the communication information and including an address of a relay point that the communication information passes through before reaching the destination of the communication information. The memory device receives the communication information, and to transmit the communication information to a next relay point, when the destination of the communication information is not the local memory device, by using the address of the relay point included in the route information of the communication information.

Abstract: An access control apparatus for controlling an access to a storage device, the access control apparatus includes a measuring unit configured to measure the time to erase data stored in the storage device, and a determination unit configured to determine a data size of an error correcting code added to data stored in the storage device in accordance with the time measured by the measuring unit. The access control apparatus includes a generation unit configured to generate the error correcting code having the data size determined by the determination unit, and an access controller configured to write the data and the error correcting code generated by the generation unit into the storage device.

Abstract: A storage device includes a programmable device into which predetermined control data is written, a control data storing unit that stores therein write control data and read control data, the write control data being control data for realizing a function to save data stored in a cache memory into a nonvolatile memory when an abnormal shut-down occurs and the read control data being control data for realizing a function to restore the data saved in the nonvolatile memory into the cache memory when an electric power source is turned on after the abnormal shut-down, a writing unit that, when an electric power source is turned on after occurrence of the abnormal shut-down of the storage device, writes the read control data into the programmable device, and a restoring instructing unit that instructs the programmable device to restore the data saved in the nonvolatile memory into the cache memory.

Abstract: A non-volatile semiconductor memory device includes: a memory unit including a plurality of memory cells, each of the plurality of memory cells to perform a multi-level storage operation by assigning a value including a plurality of bits to at least four data states defined according to a threshold level; and a controller to control the memory unit, wherein the controller sets at least one of the plurality of bits to an error correction bit that indicates one of a first state and a second state; assigns the first state to the error correction bits that correspond to the data states having a minimum threshold level and a maximum threshold level and the second state to the error correction bits that correspond to the data state having other threshold level; and resets the error correction bit to the first state when the error correction bit indicates the second state.

Abstract: Each of (n?1) 2-bit checking units, where n is an integer larger than or equal to 4, receives n-bit redundant encoded data generated from 1-bit input data, and outputs 2-bit check data based on a result of comparison between bits of the encoded data, combinations of the bits differing in each comparison. An all-bit checking unit outputs all-bit check data based on exclusive ORs of all-bit of the encoded data. An error detecting unit detects errors in the encoded data on the basis of the (n?1) sets of 2-bit check data and the all-bit check data, and outputs the input data on the basis of the result of error detection.

Abstract: A data converting method includes counting for each bit pattern among bit patterns that a data segment of a specific number of bits can assume, the number of data segments that have the bit pattern, where the data segments are segments of write_data written to a storage medium storing two types of bit values among which a first value has a higher error occurrence rate than a second value; correlating a bit pattern selected as a conversion source pattern, from among the bit patterns in descending order of count results, with a bit pattern selected as a conversion target pattern, from among the bit patterns in descending order of quantities of the second value respectively included in the bit patterns; and converting for each conversion source bit pattern, data segments having the conversion source bit pattern, into converted data segments having the correlated conversion target bit pattern.

Abstract: In an information processing system, a processor requests a first transfer control circuit to transfer data to a first memory. In response to the request from the processor, the first transfer control circuit sends the data to a second transfer control circuit. The second transfer control circuit stores in a second memory the data received from the first transfer control circuit, and also stores the data in the first memory through the first transfer control circuit.

Abstract: An information processing apparatus includes, a first storage unit, a second storage unit in which data stored in the first storage unit is backed up, and a memory controller that controls data backup operation. The memory controller divides a transfer source storage area into portions, and provides two transfer destination areas, each of the two transfer destination areas being divided into portions, backs up data in a direction from a beginning address of each divided area of the transfer source storage area to an end address thereof in one of the transfer destination areas provided for each divided area of the transfer source storage area, and backs up data in a direction from the end address of each divided area of the transfer source storage area to the beginning address thereof in the other transfer destination storage area.

Abstract: A RAID system includes a RAID controller that sends to a disc apparatus data to be encrypted by a data relay apparatus connected to the RAID controller and the disk apparatus. When receiving a data transfer request packet indicating a first receivable size, the data relay apparatus establishes a second receivable size that is equal to or greater than the first receivable size and that is a multiple of an encryption data size. When the RAID controller receives a data transfer request packet containing the established second receivable size, and in response to the data transfer request packet thus received, the data relay apparatus receives data of the second receivable size sent from the RAID controller. The data relay apparatus also encrypts the received data in units of the encryption data size, and then the encrypted data is sent to the disk apparatus in units of the first receivable size.

Abstract: A storage apparatus includes a backup processing unit that stores data stored in a first memory into a second memory as backup data upon occurrence of a power failure, a restore processing unit that upon recovery from the power failure restores the backup data backed up in the second memory to the first memory and erases the backup data, and an erasure processing termination unit that terminates the erasure processing upon a power failure occurring during erasure processing for erasing the backup data stored in the second memory, and a re-backup processing unit that re-backs up data in the first memory corresponding to the backup data erased from the second memory before the erasure processing is terminated by the erasure processing termination unit to a location in the second memory subsequent to a last location that contains the backup data which has not been erased.