Abstract: A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of ?2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.

Abstract: An input protection circuit is provided which has a high electrostatic discharge (ESD) breakdown voltage and can input a signal in a wide positive and negative voltage range. In a surface layer of a substrate, a well and a field insulating film are formed. An emitter region is formed in the well to form a lateral bipolar transistor having the well as its base. Another emitter region is formed in the surface layer of the substrate to form another lateral bipolar transistor having the well as its collector. A gate electrode layer is formed on the field insulating film between the well and the other emitter region to form a MOS transistor. The emitter region is connected to an input terminal, the well is connected to the gate electrode layer, and the other emitter region and substrate are connected to a ground potential.

Abstract: A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of ?2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.

Abstract: A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of ?2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.

Abstract: An input protection circuit is provided which has a high electrostatic discharge (ESD) breakdown voltage and can input a signal in a wide positive and negative voltage range. In a surface layer of a substrate, a well and a field insulating film are formed. An emitter region is formed in the well to form a lateral bipolar transistor having the well as its base. Another emitter region is formed in the surface layer of the substrate to form another lateral bipolar transistor having the well as its collector. A gate electrode layer is formed on the field insulating film between the well and the other emitter region to form a MOS transistor. The emitter region is connected to an input terminal, the well is connected to the gate electrode layer, and the other emitter region and substrate are connected to a ground potential.

Abstract: A drain of an n-channel MOS transistor NT1 is connected to an input terminal IN for supplying an input signal to a main circuit MC, and also a source of the transistor NT1 is connected to a reference potential Vss. A source of a p-channel MOS transistor PT1 is connected to the input terminal IN, a current limiting resistor R1 is connected between the drain of the transistor PT1 and the reference potential Vss, and a source voltage Vdd=+5 [V] is supplied to the gate of the transistor PT1. An interconnection point Q1 between the drain of the transistor PT1 and the resistor R1 is connected to the gate of the transistor NT1 directly or via a gate protecting resistor R2.

Abstract: A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of −2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.