Patents by Inventor Teruo HATADA

Teruo HATADA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10074660
    Abstract: In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: September 11, 2018
    Assignee: FLOADIA CORPORATION
    Inventors: Hideo Kasai, Yasuhiro Taniguchi, Yasuhiko Kawashima, Ryotaro Sakurai, Yutaka Shinagawa, Tatsuro Toya, Takanori Yamaguchi, Fukuo Owada, Shinji Yoshida, Teruo Hatada, Satoshi Noda, Takafumi Kato, Tetsuya Muraya, Kosuke Okuyama
  • Publication number: 20180019248
    Abstract: In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.
    Type: Application
    Filed: February 19, 2016
    Publication date: January 18, 2018
    Inventors: Hideo KASAI, Yasuhiro TANIGUCHI, Yasuhiko KAWASHIMA, Ryotaro SAKURAI, Yutaka SHINAGAWA, Tatsuro TOYA, Takanori YAMAGUCHI, Fukuo OWADA, Shinji YOSHIDA, Teruo HATADA, Satoshi NODA, Takafumi KATO, Tetsuya MURAYA, Kosuke OKUYAMA