Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Abstract: In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.

Abstract: A cache that supports sub-socket partitioning is discussed. Specifically, the cache supports different quality of service levels and victim cache line selection for a cache miss operation. The different quality of service levels allow for programmable ceiling usage and floor usage thresholds that allow for different techniques for victim cache line selection.

Abstract: Sub-socket partitioning is enabled using embodiments of the present invention. In one aspect, the memory mapping is performed to isolate memory access for each of the partitions by assigning a partition address and a generated physical address.

Abstract: A method is described that involves determining that software state information of program code is to be made visible to a monitoring system. The method also involves initiating the writing of the software state information into a register. The method also involves waiting for the software state information to be placed onto a link within a link based computing system.

Abstract: A method of booting up a computer system comprising a first multi-cored processor comprising a first plurality of cores and a second multi-cored processor comprising a second plurality of cores is disclosed. The method may comprise configuring a first partition comprising a first one or more cores from the first plurality of cores and from the second plurality of cores, configuring a second partition comprising a second one or more cores from the first plurality of cores and from the second plurality of cores, and configuring a third partition comprising a third one or more cores from the first plurality of cores and one or more cores from the second plurality of cores.

Abstract: Method and apparatus to scrub memory is disclosed. A patrol request, for example a read/write request, may be raised to the memory command scheduler in an out of order memory controller to scrub the memory. The patrol read/write request may be raised as and when patrol interval timer expires. The patrol read/write request may also be raised based on presence of a transaction in-flight to the memory, retry response from the memory command scheduler and correctable or non-correctable error response from the memory command scheduler. An interrupt may be raised to a processor upon completion response from the memory command scheduler.

Abstract: A method is described that involves within a link based computing system, opportunistically transmitting, into a network utilized by components of the link based computing system, one or more packets that contain computing system state information. The computing system state information includes software state information created through execution of software by said link based computing system. The method also involves collecting the computing system state information at a monitoring and/or debugging system attached to the link based computing system in order to analyze the link based computing system's operation.

Abstract: A power control circuit includes a selector coupled to a first power source and a second power source. The selector selects power from the first power source for powering a load based on a status signal from at least the first power source. The first power source may be an environmental power source and the second power source may be another type of power source.

Abstract: A method is described that involves determining that software state information of program code is to be made visible to a monitoring system. The method also involves initiating the writing of the software state information into a register. The method also involves waiting for the software state information to be placed onto a link within a link based computing system.

Abstract: A memory agent that communicates with another memory agent over links may include error hardware to monitor errors in the links. In some embodiments, the error hardware may include logic to classify the errors into different severity levels, control corrective action based on the severity level of errors, and/or perform various levels of reset based on the severity level of errors. Other embodiments are disclosed and claimed.

Abstract: A method is described that involves determining that software state information of program code is to be made visible to a monitoring system. The method also involves initiating the writing of the software state information into a register. The method also involves waiting for the software state information to be placed onto a link within a link based computing system.

Abstract: In one embodiment, the present invention includes a method for speculatively providing a read request to a memory controller associated with a processor, determining coherency of the read request in parallel with obtaining data of the speculatively provided read request, and providing the data of the speculatively provided read request to the processor if the read request is coherent. In this way, data may be used by a processor with a reduced latency. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for resolving conflicts, including receiving data access requests from multiple requestors at a home agent that owns the data, determining whether any of the requests are transactional requests, any of the requestors obtains the data forwarded from another agent, and a highest priority transactional requestor, and based at least in part on the determining, sending from the home agent a first message to the highest priority transactional requestor to indicate that the highest priority transactional requestor is to not abort its transaction and a second message to the other requestor to indicate that the corresponding requestor is to abort its transaction. Other embodiments are described and claimed.

Abstract: Sub-socket partitioning is enabled using embodiments of the present invention. In one aspect, the memory mapping is performed to isolate memory access for each of the partitions by assigning a partition address and a generated physical address.

Abstract: In one aspect, the issues of events that may impact one or more partitions of sub-socket partitioning in one or more sockets can be handled. Specifically, events for partitions can be handled in a socket with sub-socket partitioning, wherein the events may include reset, interrupts, errors and reliability, availability, and serviceability (RAS) management.

Abstract: Embodiments enable sub-socket partitioning that facilitates access among a plurality of partitions to a shared resource. A round robin arbitration policy is to allow each partition, within a socket, that may utilize a different operating system, access to the shared resource based at least in part on whether an assigned bandwidth parameter for each partition is consumed. Embodiments may further include support for virtual channels.

Abstract: A cache that supports sub-socket partitioning is discussed. Specifically, the cache supports different quality of service levels and victim cache line selection for a cache miss operation. The different quality of service levels allow for programmable ceiling usage and floor usage thresholds that allow for different techniques for victim cache line selection.

Abstract: A method of booting up a computer system comprising a first multi-cored processor comprising a first plurality of cores and a second multi-cored processor comprising a second plurality of cores is disclosed. The method may comprise configuring a first partition comprising a first one or more cores from the first plurality of cores and from the second plurality of cores, configuring a second partition comprising a second one or more cores from the first plurality of cores and from the second plurality of cores, and configuring a third partition comprising a third one or more cores from the first plurality of cores and one or more cores from the second plurality of cores.

Abstract: In one embodiment, a method for on-die read only memory (ROM) built-in self-test (BIST) is disclosed. The method comprises testing odd word line entries of a read-only memory (ROM) array by performing two passes through the ROM array to test each odd word line entry for static and delay faults, testing even word line entries of the ROM array by performing two passes through the ROM array to test each even word line entry for static and delay faults, and testing each entry of the ROM array for static faults masked by dynamic faults by performing two passes through the ROM array. Other embodiments are also described.