Patents by Inventor Tetsu Kachi
Tetsu Kachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190019873Abstract: A method of manufacturing a gate switching device is provided. The method includes: forming an oxide insulating layer on a gallium nitride semiconductor layer of n-type or i-type; forming a gallium oxide layer at an interface between the oxide insulating layer and the gallium nitride semiconductor layer by heating the oxide insulating layer and the gallium nitride semiconductor layer at a temperature higher than a temperature of the oxide insulating layer and the gallium nitride semiconductor layer in the formation of the oxide insulating layer; and forming a gate electrode opposed to the gallium nitride semiconductor layer via the gallium oxide layer.Type: ApplicationFiled: June 22, 2018Publication date: January 17, 2019Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, NATIONAL UNIVERSITY CORPORATION NAGOYA UNIVERSITYInventors: Koji SHIOZAKI, Tetsuo NARITA, Daigo KIKUTA, Kenta CHOKAWA, Kenji SHIRAISHI, Tetsu KACHI
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Patent number: 10121663Abstract: A semiconductor device includes a GaN device provided with: a substrate made of a semi-insulating material or a semiconductor; a channel-forming layer including a GaN layer arranged on the substrate; a gate structure in which a gate-insulating film in contact with the GaN layer is arranged on the channel-forming layer, the gate structure having a gate electrode arranged across the gate-insulating film; and a source electrode and a drain electrode that are arranged on the channel-forming layer and on opposite sides interposing the gate structure. The donor element concentration at the interface between the gate-insulating film and the GaN layer and at the lattice position on the GaN layer side with respect to the interface is set to be less than or equal to 5.0×1017 cm?3.Type: GrantFiled: March 26, 2015Date of Patent: November 6, 2018Assignee: DENSO CORPORATIONInventors: Yoshinori Tsuchiya, Hiroyuki Tarumi, Shinichi Hoshi, Masaki Matsui, Kenji Itoh, Tetsuo Narita, Tetsu Kachi
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Patent number: 9818856Abstract: A semiconductor device includes a HEMT and a diode. The HEMT includes: a substrate having a GaN layer as a channel layer generating a two-dimensional electron gas and an AlGaN layer as a barrier layer on the GaN layer; a source electrode on the AlGaN layer ohmic contacting the AlGaN layer; a drain electrode on the AlGaN layer apart from the source electrode and ohmic contacting the AlGaN layer; an inter-layer insulating film on the AlGaN layer between the source electrode and the drain electrode; and a gate electrode on the inter-layer insulating film. The substrate includes an active layer region generating the two dimensional electron gas in the GaN layer. The diode includes an anode electrically connected to the gate electrode and a cathode electrically connected to the drain electrode.Type: GrantFiled: October 17, 2012Date of Patent: November 14, 2017Assignee: DENSO CORPORATIONInventors: Shinichi Hoshi, Shoji Mizuno, Tetsu Kachi, Tsutomu Uesugi, Kazuyoshi Tomita, Kenji Ito
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Patent number: 9735260Abstract: A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm?3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.Type: GrantFiled: February 27, 2014Date of Patent: August 15, 2017Assignee: Toyota Jidosha Kabushiki KaishaInventors: Masahiro Sugimoto, Tetsu Kachi, Yoshitaka Nakano, Tsutomu Uesugi, Hiroyuki Ueda, Narumasa Soejima
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Publication number: 20170162391Abstract: A semiconductor device includes a GaN device provided with: a substrate made of a semi-insulating material or a semiconductor; a channel-forming layer including a GaN layer arranged on the substrate; a gate structure in which a gate-insulating film in contact with the GaN layer is arranged on the channel-forming layer, the gate structure having a gate electrode arranged across the gate-insulating film; and a source electrode and a drain electrode that are arranged on the channel-forming layer and on opposite sides interposing the gate structure. The donor element concentration at the interface between the gate-insulating film and the GaN layer and at the lattice position on the GaN layer side with respect to the interface is set to be less than or equal to 5.0×1017 cm?3.Type: ApplicationFiled: March 26, 2015Publication date: June 8, 2017Inventors: Yoshinori TSUCHIYA, Hiroyuki TARUMI, Shinichi HOSHI, Masaki MATSUI, Kenji ITOH, Tetsuo NARITA, Tetsu KACHI
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Patent number: 9337267Abstract: A semiconductor device is provided with an electronic transit layer, an electron supply layer, a source region, a drain electrode, a source electrode and an insulated gate. In a region between the drain electrode and the insulated gate, a two-dimensional electron gas layer is configured to be generated at a hetero junction between the electronic transit layer and the electron supply layer. A part of the insulated gate is configured to face to the source region.Type: GrantFiled: January 21, 2015Date of Patent: May 10, 2016Assignee: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHOInventors: Tsutomu Uesugi, Tetsu Kachi, Daigo Kikuta, Tetsuo Narita
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Patent number: 9184271Abstract: A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm?3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.Type: GrantFiled: June 24, 2010Date of Patent: November 10, 2015Assignee: Toyota Jidosha Kabushiki KaishaInventors: Masahiro Sugimoto, Tetsu Kachi, Yoshitaka Nakano, Tsutomu Uesugi, Hiroyuki Ueda, Narumasa Soejima
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Publication number: 20150221759Abstract: A semiconductor device is provided with an electronic transit layer, an electron supply layer, a source region, a drain electrode, a source electrode and an insulated gate. In a region between the drain electrode and the insulated gate, a two-dimensional electron gas layer is configured to be generated at a hetero junction between the electronic transit layer and the electron supply layer. A part of the insulated gate is configured to face to the source region.Type: ApplicationFiled: January 21, 2015Publication date: August 6, 2015Inventors: Tsutomu UESUGI, Tetsu KACHI, Daigo KIKUTA, Tetsuo NARITA
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Publication number: 20140231874Abstract: A semiconductor device includes a HEMT and a diode. The HEMT includes: a substrate having a GaN layer as a channel layer generating a two-dimensional electron gas and an AlGaN layer as a barrier layer on the GaN layer; a source electrode on the AlGaN layer ohmic contacting the AlGaN layer; a drain electrode on the AlGaN layer apart from the source electrode and ohmic contacting the AlGaN layer; an inter-layer insulating film on the AlGaN layer between the source electrode and the drain electrode; and a gate electrode on the inter-layer insulating film. The substrate includes an active layer region generating the two dimensional electron gas in the GaN layer. The diode includes an anode electrically connected to the gate electrode and a cathode electrically connected to the drain electrode.Type: ApplicationFiled: October 17, 2012Publication date: August 21, 2014Applicant: DENSO CORPORATIONInventors: Shinichi Hoshi, Shoji Mizuno, Tetsu Kachi, Tsutomu Uesugi, Kazuyoshi Tomita, Kenji Ito
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Publication number: 20140175518Abstract: A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm?3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.Type: ApplicationFiled: February 27, 2014Publication date: June 26, 2014Applicant: Toyota Jidosha Kabushiki KaishaInventors: Masahiro Sugimoto, Tetsu Kachi, Yoshitaka Nakano, Tsutomu Uesugi, Hiroyuki Ueda, Narumasa Soejima
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Patent number: 8299498Abstract: A semiconductor device 10 is provided with a first hetero junction 40b configured with two types of nitride semiconductors having different bandgap energy from each other, a second hetero junction 50b configured with two types of nitride semiconductors having different bandgap energy from each other, and a gate electrode 58 facing the second hetero junction 50b. The second hetero junction 50b is configured to be electrically connected to the first hetero junction 40b. The first hetero junction 40b is a c-plane and the second hetero junction 50b is either an a-plane or an m-plane.Type: GrantFiled: April 7, 2008Date of Patent: October 30, 2012Assignees: Kabushiki Kaisha Toyota Chuo Kenkyusho, Toyota Jidosha Kabushiki KaishaInventors: Tsutomu Uesugi, Kenji Ito, Osamu Ishiguro, Tetsu Kachi, Masahiro Sugimoto
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Patent number: 8222675Abstract: A nitride semiconductor device 2 comprises a nitride semiconductor layer 10. A gate insulating film 16 is formed on the surface of the nitride semiconductor layer 10. The gate insulating film 16 includes a portion composed of an aluminum nitride film 15 and a portion composed of an insulating material 14 that contains at least one of oxygen or silicon. A region W2 of the nitride semiconductor layer 10 facing the aluminum nitride film 15 is included in a region W1 of the nitride semiconductor layer 10 facing a gate electrode 18. The nitride semiconductor device 2 may further comprise a nitride semiconductor lower layer 8. The nitride semiconductor layer 10 may be stacked on the surface of the nitride semiconductor lower layer 8. The nitride semiconductor layer 10 may have a larger band gap than that of the nitride semiconductor lower layer 8 and have a heterojunction formed there between.Type: GrantFiled: August 20, 2009Date of Patent: July 17, 2012Assignee: Toyota Jidosha Kabushiki KaishaInventors: Masahiro Sugimoto, Hiroyuki Ueda, Tsutomu Uesugi, Masakazu Kanechika, Tetsu Kachi
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Patent number: 8188514Abstract: An HEMT type transistor is disclosed that is a normally off type, and in which variations in the gate threshold voltage are small. A transistor is provided with a p-type region, a barrier region, an insulation film, a gate electrode. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region. The insulation film is connected to an upper surface of the second channel region and an upper surface of the barrier region. The gate electrode faces the second channel region and the barrier region via the insulation film. The first channel region and the second channel region are arranged in series in a current pathway.Type: GrantFiled: August 12, 2009Date of Patent: May 29, 2012Assignees: Rensselaer Polytechnic Institute, Toyota Jidosha Kabushiki KaishaInventors: Masahiro Sugimoto, Tat-Sing Paul Chow, Zhongda Li, Tetsu Kachi, Tsutomu Uesugi
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Patent number: 8110870Abstract: A semiconductor device has a semiconductor substrate having a surface layer and a p-type semiconductor region, wherein the surface layer includes a contact region, a channel region and a drift region, the channel region is adjacent to and in contact with the contact region, the drift region is adjacent to and in contact with the channel region and includes n-type impurities at least in part, and the p-type semiconductor region is in contact with the drift region and at least a portion of a rear surface of the channel region, a main electrode disposed on the surface layer and electrically connected to the contact region, a gate electrode disposed on the surface layer and extending from above a portion of the contact region to above at least a portion of the drift region via above the channel region, and an insulating layer covering at least the portion of the contact region and not covering at least the portion of the drift region.Type: GrantFiled: July 14, 2009Date of Patent: February 7, 2012Assignee: Toyota Jidosha Kabushiki KaishaInventors: Masahiro Sugimoto, Tsutomu Uesugi, Masakazu Kanechika, Tetsu Kachi
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Patent number: 8008749Abstract: A semiconductor device is provided with a drain electrode 22, a semiconductor base plate 32, an electric current regulation layer 42 covering a part of a surface of the semiconductor base plate 32 and leaving a non-covered surface 55 at the surface of the semiconductor base plate 32, a semiconductor layer 50 covering a surface of the electric current regulation layer 42, and a source electrode 62 formed at a surface of the semiconductor layer 50. A drift region 56, a channel forming region 54, and a source region 52 are formed within the semiconductor layer 50. The drain electrode 22 is connected to a first terminal of a power source, and the source electrode 62 is connected to a second terminal of the power source. With this semiconductor layer 50, it is possible to increase withstand voltage or reduce the occurrence of current leakage.Type: GrantFiled: November 14, 2005Date of Patent: August 30, 2011Assignee: Toyota Jidosha Kabushiki KaishaInventors: Masahiro Sugimoto, Tsutomu Uesugi, Hiroyuki Ueda, Narumasa Soejima, Tetsu Kachi
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Patent number: 7897987Abstract: A light-emitting device includes a light-emitting diode, a red light-emitting phosphor layer, a yellow light-emitting phosphor layer, and a blue light-emitting phosphor layer. These layers are stacked in the stacking sequence of the yellow, blue, and red phosphor layers in order of increasing distance from the LED. The stacking sequence of the yellow and blue phosphor layers is first determined in such a manner that these layers do not interact with each other. The stacking sequence of the red and yellow phosphor layers and the stacking sequence of the red and blue phosphor layers are determined by the discriminant D. This determination of the stacking sequence suppresses a reduction in the conversion efficiency of the phosphors due to concentration quenching, improving the emission efficiency of the light-emitting device.Type: GrantFiled: March 6, 2009Date of Patent: March 1, 2011Assignee: Toyoda Gosei Co., Ltd.Inventors: Mitsuhiro Inoue, Kenji Ito, Kazuyohi Tomita, Tetsu Kachi, Takahiro Kozawa, Satoru Kato, Tadashi Ichikawa
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Publication number: 20100295098Abstract: A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm?3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.Type: ApplicationFiled: June 24, 2010Publication date: November 25, 2010Applicant: Toyota Jidosha Kabushiki KaishaInventors: Masahiro SUGIMOTO, Tetsu KACHI, Yoshitaka NAKANO, Tsutomu UESUGI, Hiroyuki UEDA, Narumasa SOEJIMA
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Patent number: 7800130Abstract: A semiconductor device 10 comprises a heterojunction between a lower semiconductor layer 26 made of p-type gallium nitride and an upper semiconductor layer 28 made of n-type AlGaN, wherein the upper semiconductor layer 28 has a larger band gap than the lower semiconductor layer 26. The semiconductor device 10 further comprises a drain electrode 32 formed on a portion of a top surface of the upper semiconductor layer 28, a source electrode 34 formed on a different portion of the top surface of the upper semiconductor layer 28, and a gate electrode 36 electrically connected to the lower semiconductor layer 26. The semiconductor device 10 can operate as normally-off.Type: GrantFiled: January 20, 2006Date of Patent: September 21, 2010Assignee: Toyota Jidosha Kabushiki KaishaInventors: Masahiro Sugimoto, Tetsu Kachi, Tsutomu Uesugi, Hiroyuki Ueda, Narumasa Soejima
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Patent number: 7777252Abstract: A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm?3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.Type: GrantFiled: June 22, 2005Date of Patent: August 17, 2010Assignee: Toyota Jidosha Kabushiki KaishaInventors: Masahiro Sugimoto, Tetsu Kachi, Yoshitaka Nakano, Tsutomu Uesugi, Hiroyuki Ueda, Narumasa Soejima
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Publication number: 20100117119Abstract: A semiconductor device 10 is provided with a first hetero junction 40b configured with two types of nitride semiconductors having different bandgap energy from each other, a second hetero junction 50b configured with two types of nitride semiconductors having different bandgap energy from each other, and a gate electrode 58 facing the second hetero junction 50b. The second hetero junction 50b is configured to be electrically connected to the first hetero junction 40b. The first hetero junction 40b is a c-plane and the second hetero junction 50b is either an a-plane or an m-plane.Type: ApplicationFiled: April 7, 2008Publication date: May 13, 2010Applicants: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Tsutomu Uesugi, Kenji Ito, Osamu Ishiguro, Tetsu Kachi, Masahiro Sugimoto