Abstract: A data slicer for converting an envelope signal of an amplitude-modulated wave into a binary signal, comprises: an average level generation circuit configured to generate an average level of the envelope signal by averaging the envelope signal per time; a fixed voltage value generation circuit configured to generate a fixed voltage value; a reference level generation circuit configured to generate a reference level in accordance with the fixed voltage value and the average level of the envelope signal; and a comparison circuit configured to compare a signal level of the envelope signal with the reference level to output a result of the comparison as the binary signal.

Abstract: A flag holding circuit includes: a flag setting part connected to a voltage supply line and charging a capacitor according to an input signal; a flag determination part outputting an output signal based on a charging voltage of the capacitor; and a discharging part discharging the capacitor. The flag setting part includes: a switch having a first terminal connected to a connection line between the flag determination part and the discharging part and a second terminal connected to the voltage supply line or a grounding line according to a signal level of the input signal, and connecting or disconnecting the voltage supply line or the grounding line with the connection line according to a leakage control signal; and a switch control part, generating the leakage control signal whose signal level changes to be greater than a power supply voltage according to a clock signal and supplying it to the switch.

Abstract: A semiconductor device and a method of generating a power on reset signal that can reliably perform power on reset on an internal circuit and subsequently cancel the reset state regardless of environmental temperature are provided. The semiconductor device according to the disclosure includes: a voltage divider circuit dividing a power supply voltage to obtain first and second voltages having different voltage values; a first transistor receiving the first voltage at the control electrode to generate a first current; a second transistor receiving the second voltage at the control electrode to generate a second current; a current comparing part comparing the first and second currents to generate a current comparison result signal representing a comparison result; and a reset signal generating part generating a power on reset signal having a first level that prompts reset or a second level that prompts reset cancelation based on the current comparison result signal.

Abstract: A flag retaining circuit comprises a first capacitor element having one end connected to a first line and the other end grounded; a flag setting unit that charges the first capacitor element according to an input signal; a flag checking unit that outputs 0 or 1 based on the potential of the first capacitor element; and a discharging unit that discharges the first capacitor element. The discharging unit includes a transconductance element that discharges the first capacitor element via the first line; a control switch that receives supply of the voltage on a second line; and a second capacitor element having one end connected to a node between a control input end of the transconductance element and the control switch, and the other end grounded. The flag checking unit outputs the inverse of the voltage on the first line onto the second line.

Abstract: A data slicer for converting an envelope signal of an amplitude-modulated wave into a binary signal, comprises: an average level generation circuit configured to generate an average level of the envelope signal by averaging the envelope signal per time; a fixed voltage value generation circuit configured to generate a fixed voltage value; a reference level generation circuit configured to generate a reference level in accordance with the fixed voltage value and the average level of the envelope signal; and a comparison circuit configured to compare a signal level of the envelope signal with the reference level to output a result of the comparison as the binary signal.

Abstract: A semiconductor device and a method of generating a power on reset signal that can reliably perform power on reset on an internal circuit and subsequently cancel the reset state regardless of environmental temperature are provided. The semiconductor device according to the disclosure includes: a voltage divider circuit dividing a power supply voltage to obtain first and second voltages having different voltage values; a first transistor receiving the first voltage at the control electrode to generate a first current; a second transistor receiving the second voltage at the control electrode to generate a second current; a current comparing part comparing the first and second currents to generate a current comparison result signal representing a comparison result; and a reset signal generating part generating a power on reset signal having a first level that prompts reset or a second level that prompts reset cancelation based on the current comparison result signal.

Abstract: A flag retaining circuit comprises a first capacitor element having one end connected to a first line and the other end grounded; a flag setting unit that charges the first capacitor element according to an input signal; a flag checking unit that outputs 0 or 1 based on the potential of the first capacitor element; and a discharging unit that discharges the first capacitor element. The discharging unit includes a transconductance element that discharges the first capacitor element via the first line; a control switch that receives supply of the voltage on a second line; and a second capacitor element having one end connected to a node between a control input end of the transconductance element and the control switch, and the other end grounded. The flag checking unit outputs the inverse of the voltage on the first line onto the second line.

Abstract: A flag holding circuit includes: a flag setting part connected to a voltage supply line and charging a capacitor according to an input signal; a flag determination part outputting an output signal based on a charging voltage of the capacitor; and a discharging part discharging the capacitor. The flag setting part includes: a switch having a first terminal connected to a connection line between the flag determination part and the discharging part and a second terminal connected to the voltage supply line or a grounding line according to a signal level of the input signal, and connecting or disconnecting the voltage supply line or the grounding line with the connection line according to a leakage control signal; and a switch control part, generating the leakage control signal whose signal level changes to be greater than a power supply voltage according to a clock signal and supplying it to the switch.

Abstract: A high-frequency amplifier circuit comprising a first and a second amplification units connected in cascade structure and so on. The first amplification unit includes an FET of a first conductivity type having a source terminal supplied with a first potential, and a first inductor connected to an intermediate potential line, and the second amplification unit includes an FET of a second conductivity type having a source terminal supplied with a second potential, and a second inductor connected to the intermediate potential line. The intermediate potential line is supplied with an intermediate potential between the first and second potentials. The first and second amplification units are supplied with bias voltages by a first and a second bias units, respectively. An operating current for the second bias unit is controlled on the basis of the intermediate potential.

Abstract: Provided are a power supply device capable of producing a highly-accurate supply voltage at low power consumption, a method for controlling the power supply device, and an electronic apparatus in which the power supply device is incorporated. The power supply device includes a first power supplying part and a second power supplying part which has less output current capacity than the first power supplying part does. The power supply device is configured to control the voltage value of the second voltage produced in the second power supplying part in order to make the first voltage produced in the first power supplying part equal to the second voltage produced in the second power supplying part.

Abstract: A high-frequency amplifier circuit comprising a first and a second amplification units connected in cascade structure and so on. The first amplification unit includes an FET of a first conductivity type having a source terminal supplied with a first potential, and a first inductor connected to an intermediate potential line, and the second amplification unit includes an FET of a second conductivity type having a source terminal supplied with a second potential, and a second inductor connected to the intermediate potential line. The intermediate potential line is supplied with an intermediate potential between the first and second potentials. The first and second amplification units are supplied with bias voltages by a first and a second bias units, respectively. An operating current for the second bias unit is controlled on the basis of the intermediate potential.

Abstract: A gm-C VCO oscillates at a frequency that corresponds to an input control voltage. A divider divides the frequency of an oscillation signal output from the gm-C VCO. A phase comparison signal generating unit generates a phase difference signal that corresponds to the phase difference between the oscillation signal thus frequency-divided by the divider and a reference clock signal. A loop filter performs filtering of the phase difference signal so as to generate the control voltage. A startup circuit injects a seed pulse into the gm-C VCO at a timing determined based upon the level of a detection signal that corresponds to the control voltage.

Abstract: A gm-C VCO oscillates at a frequency that corresponds to an input control voltage. A divider divides the frequency of an oscillation signal output from the gm-C VCO. A phase comparison signal generating unit generates a phase difference signal that corresponds to the phase difference between the oscillation signal thus frequency-divided by the divider and a reference clock signal. A loop filter performs filtering of the phase difference signal so as to generate the control voltage. A startup circuit injects a seed pulse into the gm-C VCO at a timing determined based upon the level of a detection signal that corresponds to the control voltage.

Abstract: Regarding N-channel first transistor and a P-channel second transistor, their first terminals are connected to each other and their second terminals are connected to each other. Regarding third transistor and a fourth transistor, their first terminals are also connected to each other and their second terminals are also connected to each other. For the first transistor through the fourth transistor, a first capacitor through a fourth capacitor used for coupling are provided. A first impedance element through a fourth impedance element are provided in a path where a bias voltage is applied to the first transistor through the fourth transistor. A fifth capacitor is provided between the first terminals of the first-fourth transistors and a first input terminal. A fifth impedance element and a sixth impedance element are provided as differential pair loads.

Abstract: Regarding N-channel first transistor and a P-channel second transistor, their first terminals are connected to each other and their second terminals are connected to each other. Regarding third transistor and a fourth transistor, their first terminals are also connected to each other and their second terminals are also connected to each other. For the first transistor through the fourth transistor, a first capacitor through a fourth capacitor used for coupling are provided. A first impedance element through a fourth impedance element are provided in a path where a bias voltage is applied to the first transistor through the fourth transistor. A fifth capacitor is provided between the first terminals of the first-fourth transistors and a first input terminal. A fifth impedance element and a sixth impedance element are provided as differential pair loads.