Patents by Inventor Tetsuhiko Endo
Tetsuhiko Endo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7941730Abstract: A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.Type: GrantFiled: May 31, 2006Date of Patent: May 10, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Toshio Ogawa, Yoshihiro Takemae, Yoshinori Okajima, Tetsuhiko Endo, Yasuro Matsuzaki
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Patent number: 7937645Abstract: A conversion control unit sets a converting function of a write data conversion unit or a read data conversion unit enabled or disabled for each controller. Accordingly, for a controller which needs original external data, the external data can be inputted and outputted, whereas for a controller which needs converted internal data, the internal data can be inputted and outputted. A data converting function of a conventional controller can be realized in a semiconductor memory, which can reduce the load on the controller. As a result, the performance of a system can be improved. A disabled controller which has no access right cannot read correct data (original data before conversion). Hence, the security of data written into the semiconductor memory can be protected.Type: GrantFiled: May 31, 2006Date of Patent: May 3, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Toshio Ogawa, Yoshihiro Takemae, Yoshinori Okajima, Tetsuhiko Endo, Yasuro Matsuzaki
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Patent number: 7561455Abstract: A controller converts a parallel command signal and address signal, or a parallel write data signal into a first serial signal, and outputs the converted signal as a first optical signal with a single wavelength to a memory device via an optical transmission line. The memory device converts the first optical signal into the original parallel command signal, address signal, and write data signal, and outputs the converted parallel signals to a memory unit. The memory device converts a parallel read data signal from the memory unit into a second serial signal, and outputs the converted signal to the controller via the optical transmission line as a second optical signal with a single wavelength. It is unnecessary to transmit the optical signal using an optical multiplexer, an optical demultiplexer, etc., thereby improving transmission rate of signals transmitted between the controller and the memory device at minimum cost.Type: GrantFiled: August 3, 2006Date of Patent: July 14, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Toshio Ogawa, Yoshihiro Takemae, Yoshinori Okajima, Tetsuhiko Endo, Yasuro Matsuzaki
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Patent number: 7417884Abstract: A memory controller multiplexes access signals each consisting of a plurality of bits as optical signals and outputs the multiplexed optical signals. At this time, the optical signals whose wavelengths differ depending on memory devices are generated. A memory interface unit demultiplexes the multiplexed optical signals into the original optical signals and converts the demultiplexed optical signals into electrical signals. The memory interface unit determines to which of the memory devices the electrical signals resulting from the conversion should be outputted, according to the wavelengths of the demultiplexed optical signals. This frees the memory controller from a need for transmitting to the memory interface unit a signal for identifying the memory device. The memory interface unit need not include a decoding circuit for identifying the memory device.Type: GrantFiled: May 31, 2006Date of Patent: August 26, 2008Assignee: Fujitsu LimitedInventors: Toshio Ogawa, Yoshihiro Takemae, Yoshinori Okajima, Tetsuhiko Endo, Yasuro Matsuzaki
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Publication number: 20070230231Abstract: A controller converts a parallel command signal and address signal, or a parallel write data signal into a first serial signal, and outputs the converted signal as a first optical signal with a single wavelength to a memory device via an optical transmission line. The memory device converts the first optical signal into the original parallel command signal, address signal, and write data signal, and outputs the converted parallel signals to a memory unit. The memory device converts a parallel read data signal from the memory unit into a second serial signal, and outputs the converted signal to the controller via the optical transmission line as a second optical signal with a single wavelength. It is unnecessary to transmit the optical signal using an optical multiplexer, an optical demultiplexer, etc., thereby improving transmission rate of signals transmitted between the controller and the memory device at minimum cost.Type: ApplicationFiled: August 3, 2006Publication date: October 4, 2007Inventors: Toshio Ogawa, Yoshihiro Takemae, Yoshinori Okajima, Tetsuhiko Endo, Yasuro Matsuzaki
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Publication number: 20070189100Abstract: A memory cell array ARY includes a plurality of sub-arrays SARY. A data transfer unit DTU alternately accesses the sub-arrays SARY to transfer data between the sub-arrays SARY. Accordingly, it is possible to transfer data stored in one of the sub-arrays SARY to another sub-array SARY without outputting the data to a bus connected to a semiconductor memory MEM. For example, a microcontroller CNT in a system MSYS can use the bus during the data transfer since the bus is not used for the data transfer. As a result, it is possible to prevent the performance of the system MSYS from being deteriorated due to the data transfer.Type: ApplicationFiled: May 31, 2006Publication date: August 16, 2007Inventors: Toshio Ogawa, Yoshihiro Takemae, Yoshinori Okajima, Tetsuhiko Endo, Yasuro Matsuzaki
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Publication number: 20070192664Abstract: A conversion control unit sets a converting function of a write data conversion unit or a read data conversion unit enabled or disabled for each controller. Accordingly, for a controller which needs original external data, the external data can be inputted and outputted, whereas for a controller which needs converted internal data, the internal data can be inputted and outputted. A data converting function of a conventional controller can be realized in a semiconductor memory, which can reduce the load on the controller. As a result, the performance of a system can be improved. A disabled controller which has no access right cannot read correct data (original data before conversion). Hence, the security of data written into the semiconductor memory can be protected.Type: ApplicationFiled: May 31, 2006Publication date: August 16, 2007Inventors: Toshio Ogawa, Yoshihiro Takemae, Yoshinori Okajima, Tetsuhiko Endo, Yasuro Matsuzaki
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Publication number: 20070189052Abstract: A memory controller multiplexes access signals each consisting of a plurality of bits as optical signals and outputs the multiplexed optical signals. At this time, the optical signals whose wavelengths differ depending on memory devices are generated. A memory interface unit demultiplexes the multiplexed optical signals into the original optical signals and converts the demultiplexed optical signals into electrical signals. The memory interface unit determines to which of the memory devices the electrical signals resulting from the conversion should be outputted, according to the wavelengths of the demultiplexed optical signals. This frees the memory controller from a need for transmitting to the memory interface unit a signal for identifying the memory device. The memory interface unit need not include a decoding circuit for identifying the memory device.Type: ApplicationFiled: May 31, 2006Publication date: August 16, 2007Inventors: Toshio Ogawa, Yoshihiro Takemae, Yoshinori Okajima, Tetsuhiko Endo, Yasuro Matsuzaki
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Publication number: 20070192527Abstract: A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.Type: ApplicationFiled: May 31, 2006Publication date: August 16, 2007Inventors: Toshio Ogawa, Yoshihiro Takemae, Yoshinori Okajima, Tetsuhiko Endo, Yasuro Matsuzaki
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Patent number: 4451007Abstract: A yarn winding apparatus comprises a rotating drum having a winding part rotatable at a predetermined peripheral speed for winding yarn around a peripheral surface thereof, a transferring part for successively transferring the yarn as wound around the winding part, and a storage part for storing the yarn as fed by the transferring part, the winding, transferring and storage portions being disposed adjacent to one another in the order named, a toothed wheel for catching the continuously supplied yarn around the rotating drum, and a yarn guide for guiding the continuously supplied yarn onto the winding part of the rotating drum. The yarn layers as wound on the winding part are to be discharged successively to the storage part through the transfer part so that the yarn winding speed can be kept always substantially equal to the peripheral speed of the winding part.Type: GrantFiled: September 23, 1983Date of Patent: May 29, 1984Assignee: Toray Industries, Inc.Inventors: Tadahiko Ohkubo, Tetsuhiko Endo, Akiwo Andoh
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Patent number: 4398386Abstract: A process and an apparatus for simultaneously drawing and false-twisting a thermoplastic synthetic yarn, in or by which an undrawn or a partially drawn yarn is drawn under a dry hot condition in a condition of the yarn being false-twisted by twist transmitted from a false-twister and immediately thereafter heat-set under a wet hot condition prior to untwisting.The apparatus includes a yarn heater, which comprises a dry heater disposed on the side of a feeding device for the undrawn or partially drawn yarn and a wet heater on the side of a false-twister along the yarn passing direction.Type: GrantFiled: April 20, 1981Date of Patent: August 16, 1983Assignee: Toray Industries, Inc.Inventors: Tetsuhiko Endo, Kunihiko Ueda, Tadashi Kohara
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Patent number: 4183123Abstract: Disclosed is a yarn texturing apparatus for producing a multifilament yarn containing complex interfilament entanglement, comprising a housing having inlet and outlet ends connected by a yarn passage, a turbulence section in the yarn passage, an exit orifice constituting the yarn outlet and communicating with the turbulence section and means for introducing pressurized gas into the yarn passage, which is improved by providing a yarn guide for separating a multifilament yarn blown out of the exit orifice from blown gas while guiding the yarn along a guide surface of the yarn guide. The yarn guide is provided outside of the housing and in the proximity of the exit end of the orifice, in a condition such that the yarn guide does not cross the center-line of the exit orifice and the guide surface of the yarn guide faces the yarn outlet end surface of the housing.Type: GrantFiled: December 15, 1977Date of Patent: January 15, 1980Assignee: Toray Industries, Inc.Inventors: Kenzo Tanaka, Tetsuhiko Endo
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Patent number: 4116393Abstract: A sample yarn-collecting apparatus for preparing a continuous yarn knotted in an end-to-end manner, in which sample yarns having a certain length are collected from a plurality of yarn packages, each of them are connected in succession in an end-to-end manner to obtain one continuous yarn, and the continuous yarn is wound temporarily and thereafter continuously unwound to be fed to testing means while storing it in a quantity within a predetermined range, is disclosed. This apparatus comprises sample yarn collecting means for collecting sample yarns from packages and connecting each of them to form one continuous yarn, means for storing the continuous yarn fed from said collecting means on a rotary member by winding it and feeding the continuous yarn wound and stored on the rotary member to testing means by unwinding it, and supplementary means for controlling the above two means.Type: GrantFiled: October 11, 1977Date of Patent: September 26, 1978Assignee: Toray Industries, Inc.Inventors: Yoshinori Inouye, Hiromitsu Kanamori, Nobuo Tsuchida, Syozo Morishita, Tetsuhiko Endo
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Patent number: 4040240Abstract: A method and apparatus for doubling and twisting a material yarn by a two-step changeover system by utilizing a pot twisting and winding device is disclosed. To produce a doubled and twisted yarn having a yarn configuration of two component yarns forming the yarn in a balanced condition, when the second step operation is carried out so as to double a primary twisted yarn of a yarn package formed in the pot by a first step operation with a yarn fed from a supply source and twist this doubled yarn while eliminating the primary twists imparted to the material yarn, the position of the bottom end of the traverse tube in the pot must be controlled so as to satisfy a particular condition D.sub.2 .gtoreq. L.sub.2, where D.sub.2 represents an inside diameter of the full size yarn package formed in the pot by the first step operation, while L.sub.2 represents a distance between the bottom end of the traverse tube and an inside bottom surface of the pot.Type: GrantFiled: August 12, 1976Date of Patent: August 9, 1977Assignee: Toray Industries, Inc.Inventors: Kotaro Fujioka, Osami Tsuchihashi, Tetsuhiko Endo, Masakazu Hirota