Abstract: A video controller for a personal computing system. The controller compensates CRT video information to generate a display compatible with a flat panel device. The controller includes registers and logic circuits which compensate CRT address information. The compensated addresses are used to repeat lines of display, insert blank lines between lines of display, center a display, and force font types.

Abstract: A video display controller capable of providing video control information for either a flat panel or a CRT display. The controller includes a plurality of main circuits, alternate circuits, select circuits, and a circuit for identifying the display device used in the system. Each main circuit receives information from the processor and generates main video information compatible with a CRT. Each alternate circuit receives information from the processor and generates alternate video information compatible with a flat panel display. Each select circuit receives main and alternate video information and outputs main video information when the display device is a CRT display and the alternate video information when the display device is a flat panel display. In one embodiment, the alternate circuits are programmable registers. In another embodiment, tables are used to program the alternate registers to provide compatibility for a number of possible display devices.

Abstract: A controller for providing O to N gray scales at a monochrome display. The monochrome display is of the type having an array of pixels energized by a display voltage over time to generate the gray scales. The controller generates a baseline time and uses the baseline time to provide gray scales at the display. In particular, each pixel is energized at least the baseline time for any gray scale above level 0 to reduce flicker in the display. In one embodiment, the baseline time corresponds to a point on the intensity response curve for the display at which the display exhibits a linear intensity response for a given display voltage versus time. In one embodiment, the baseline time is used to generate pixel on/off data to provide gray scales at the display. In yet another embodiment, the baseline time information is used to generate weighted clock information to provide gray scales at the display.

Abstract: A data processing system includes a video controller and a flat panel display system. The flat panel display system includes first and second flat panel displays adapted so as to appear to be essentially a single display. The video controller includes a first and second address generator for generating first and second address information and a counter for counting vertical sync position to identify alternating first and second display frames. The controller outputs the first address information to drive the first display and the second address information to drive the second display during the first display frames and outputs the second address information to drive the first display and the first address information to drive the second display during the second display frames. The displays are identical and the address generators are identical. The use of dual displays with dual, flip-flopping address generators is more advantageous than using a single address generator to drive two display panels.

Abstract: A graphics display controller equipped with a boundary search circuit is disclosed. There is provided a mask information generator generating mask information consisting of a plurality of bits in response to control data, at least one bit of the mask information taking non-mask data and the remaining bits thereof taking mask data. Each bit data of the mask information is supplied to the associated one of a plurality of mask gates along with the associated bit data of display data of one word read from a display memory. Each of the mask gates outputs the associated bit data of the display data when the associated mask information bit data is the non-mask data. The output data of the mask gates are supplied to a position information generator wherein the position information relative to a position of a bit taking a predetermined logic level is generated.

Abstract: A multiplication circuit comprises a zero detector coupled to a multiplier register so as to generate a signal indicative of completion of the multiplication operation when all of predetermined bits of the multiplier register are zero. A right shifter is coupled to the multiplier register so as to shift the input data one bit rightwardly and to put "0" at its most significant bit. The right shifter rewrites the multiplier register with the shifted data having the MSB of "0". Further, a left shifter is coupled to a multiplicand register so as to shift the input data one bit leftwardly and to put "0" at its least significant bit. The left shifter rewrites the multiplicand register with the leftwardly shifted data having the LSB of "0".

Abstract: An information processing apparatus having a mask operation includes a first circuit generating a first mask control signal indicating a start bit position of a data to be processed and a second circuit generating a second mask control signal indicating an end bit position of that data. The first mask control signal and the second mask control signal are applied to a gate circuit by which a non-mask signal is produced for a bit or bits from the start bit position to the end bit position and a mask signal is produced for the other bit or bits.

Abstract: The invention selectively designates a specific portion of information which is stored in a memory to identify information which is to be corrected. It further enables a correction of only the suitably designated portion. The read out of information having the corrected information is set in a state which is ready for use. Accordingly, it is not necessary to use a bit addressing circuit, as used in the prior art, this simplifying both the circuit design and the wiring. It is also possible to designate more than one arbitrary item of information as portions which are to be corrected and then to correct all designated information simultaneously. Thus, the read out information is corrected at a high speed. In addition, the number of information items which are capable of correction is not limited by unnecessary bit addressing. This enables an increase in the number of memory elements, and makes the system quite useful as a control device for CRT display systems.

Abstract: An information processing apparatus employs first and second direct memory access controllers which cooperate during transfer of information between first and second devices, e.g. memories. The first controller controls information transfer from the first memory to the second controller and the second controller transfers the information from its own internal storage to the second memory while simultaneously receiving further information under the control of the first controller. The second controller includes address control circuitry for high speed generation of non-sequential addresses for writing into the second memory.

Abstract: A display control system has a memory for storing display information and a memory access circuit for reading display information out of this memory. This memory access circuit includes a first circuit in which a memory address is set, a second circuit for sequentially varying the memory address by a predetermined value, and a third circuit for adding to the memory address a preset value, which is different from the predetermined value. A control circuit gives a designation of the addresses to the memory, as a result of the cooperation of the second circuit and the third circuit. The control circuit can be achieved so that display information is read while a memory address may be varied by at least two different means (the second and third circuits above). Thus, it becomes possible to selectively designate a part of a memory region and to display the information of the selected memory region.

Abstract: A picture image producing apparatus has a control unit for designating picture image calculation, a display unit for displaying a picture image, and a processing unit for storing standard information used in the picture image calculation. The standard information is x-coordinate data and y-coordinate data of the picture image to be displayed. A first calculator computes a first group information of the picture image, in response to vary the x-coordinate data of the standard information. A second calculation computes second group information of the picture image in response to the varying y-coordinate data of the standard information. The picture image information of the first and second group information is transferred to the display unit.

Abstract: An image pattern control system of the type having a dynamic memory which operates during a first period to read and rewrite the contents of memory according to address data sent from an address register and to refresh stored data according to the output of a refresh counter during a subsequent second period. The first and second periods are switched according to the output of a zoom ratio hold register.

Abstract: A binary full adder/subtractor circuit includes an exclusive OR gate operating upon augend/minuend and addend/subtrahend binary input signals. The sum/difference output from the circuit is the carry/borrow input signal or its inverse depending upon the output state of the exclusive OR gate. The carry/borrow output of the circuit comprises either the carry/borrow input or the addend/subtrahend input, as determined by the output of the exclusive OR gate and by an operation (sum/difference) specifying input signal.