Abstract: An image processing apparatus able to encode and decode images by a low cost, small sized circuit configuration, having a temporary storage portion for temporarily storing data, an encoding/decoding processing portion for reading and writing data successively with respect to the temporary storage portion and encoding and decoding the image data in parallel, and a storage control portion for controlling the read and write operations of the data with respect to the temporary storage portion, wherein the storage control portion controls the read and write operations with respect to the temporary storage portion by the encoding/decoding processing portion in the encoding processing and at least read and write operations to the temporary storage portion by the encoding/decoding processing portion in the decoding processing so as to be performed within one frame's worth or one field's worth of processing period in a time division manner.

Abstract: A data stream inputted to the inventive system from the outside is supplied to a PID (packet ID) extracting circuit 1, in which a PID is detected from a transport stream TS regardless of whether the transport stream TS is a full transport stream TS or a partial transport stream TS. The PID extracting circuit 1 transmits the thus extracted PID and data stream to a TS replacing/deleting circuit 2. The TS replacing/deleting circuit 2 has n 188-byte buffers and is able to set replaced TS packets to the buffers. A control circuit 3 such as a CPU (central processing unit) designates m PIDs relative to the respective buffers and designates the respective PIDs as the PID of the packet to be deleted or the PID of the packet to be replaced. Then, the TS replacing/deleting circuit 2 compares the PID received from the PID extracting circuit 1 with the PID designated by the control circuit 3.

Abstract: An image processing apparatus able to encode and decode images by a low cost, small sized circuit configuration, having a temporary storage portion for temporarily storing data, an encoding/decoding processing portion for reading and writing data successively with respect to the temporary storage portion and encoding and decoding the image data in parallel, and a storage control portion for controlling the read and write operations of the data with respect to the temporary storage portion, wherein the storage control portion controls the read and write operations with respect to the temporary storage portion by the encoding/decoding processing portion in the encoding processing and at least read and write operations to the temporary storage portion by the encoding/decoding processing portion in the decoding processing so as to be performed within one frame's worth or one field's worth of processing period in a time division manner.

Abstract: An image processing apparatus able to encode and decode images by a low cost, small sized circuit configuration, having a temporary storage portion for temporarily storing data, an encoding/decoding processing portion for reading and writing data successively with respect to the temporary storage portion and encoding and decoding the image data in parallel, and a storage control portion for controlling the read and write operations of the data with respect to the temporary storage portion, wherein the storage control portion controls the read and write operations with respect to the temporary storage portion by the encoding/decoding processing portion in the encoding processing and at least read and write operations to the temporary storage portion by the encoding/decoding processing portion in the decoding processing so as to be performed within one frame's worth or one field's worth of processing period in a time division manner.

Abstract: An image processing apparatus able to encode and decode images by a low cost, small sized circuit configuration, having a temporary storage portion for temporarily storing data, an encoding/decoding processing portion for reading and writing data successively with respect to the temporary storage portion and encoding and decoding the image data in parallel, and a storage control portion for controlling the read and write operations of the data with respect to the temporary storage portion, wherein the storage control portion controls the read and write operations with respect to the temporary storage portion by the encoding/decoding processing portion in the encoding processing and at least read and write operations to the temporary storage portion by the encoding/decoding processing portion in the decoding processing so as to be performed within one frame's worth or one field's worth of processing period in a time division manner.

Abstract: A data stream inputted to the inventive system from the outside is supplied to a PID (packet ID) extracting circuit 1, in which a PID is detected from a transport stream TS regardless of whether the transport stream TS is a full transport stream TS or a partial transport stream TS. The PID extracting circuit 1 transmits the thus extracted PID and data stream to a TS replacing/deleting circuit 2. The TS replacing/deleting circuit 2 has n 188-byte buffers and is able to set replaced TS packets to the buffers. A control circuit 3 such as a CPU (central processing unit) designates m PIDs relative to the respective buffers and designates the respective PIDs as the PID of the packet to be deleted or the PID of the packet to be replaced. Then, the TS replacing/deleting circuit 2 compares the PID received from the PID extracting circuit 1 with the PID designated by the control circuit 3.

Abstract: A demultiplexer, capable of extracting specific individual data from among packets in which the specific individual data is stored in predetermined units with a high efficiency, for A packet demultiplexer demultiplexes first to third packets and an extractor extracts additional information from the third pocket. The extractor has a first comparator for comparing control data in a harder region of the third packet and first comparison data based on mask data, and a second comparing comparator for comparing the control data and second comparison data based on the first comparison data and the mask data. The additional information is extracted from the third packet when the result of comparison of the first comparator indicates coincidence and result of comparison of the second comparator indicates noncoincidence.

Abstract: A system and method for flexibly blending multiple image planes in a video device comprises a timing controller configured to generate adjusted synchronization signals for pretiming multiple video image planes. The timing controller preferably generates the adjusted synchronization signals in response to programmable delay signals and a master synchronization signal. A blender device then receives and flexibly combines the multiple video image planes to generate a synchronized composite blender output signal. The blender preferably includes a selectable pseudo-output signal that may be routed through an external processing device, and returned as a feedback loop to an external input of the blender device.