Abstract: A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.

Abstract: A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.

Abstract: A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.

Abstract: A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.

Abstract: A semiconductor device containing a dielectric capacitor having an excellent step coverage for a device structure of high aspect ratio corresponding to high integration degree, as well as a manufacturing method therefor are provided. A dielectric capacitor of high integration degree is manufactured by forming a bottom electrode 46 and a top-electrode 48 comprising a homogeneous thin Ru film with 100% step coverage while putting a dielectric 47 therebetween on substrates 44, 45 having a three-dimensional structure with an aspect ratio of 3 or more by a MOCVD process using a cyclopentadienyl complex within a temperature range from 180° C. or higher to 250° C. or lower.

Abstract: A ferroelectric capacitor of the type having a top electrode, a ferroelectric thin film, and a bottom electrode, is characterized in that said ferroelectric thin film is a perovskite-type oxide containing Pb and said upper and bottom electrodes contain an intermetallic compound composed of Pt and Pb. An electronic device is provided with said ferroelectric capacitor. This construction is designed to solve the following problems. In a non-volatile ferroelectric memory (FeRAM), a degraded layer occurs near the interface between the PZT and the electrode due to hydrogen evolved during processing or due to diffusion of Pb from the PZT into the electrode. A stress due to a difference in lattice constant occurs in the interface between the electrode and the ferroelectric thin film. The degraded layer and the interfacial stress deteriorate the initial polarizing characteristics of the ferroelectric capacitor and also greatly deteriorate the polarizing characteristics after switching cycles.

Abstract: A semiconductor device containing a dielectric capacitor having an excellent step coverage for a device structure of high aspect ratio corresponding to high integration degree, as well as a manufacturing method therefor are provided. A dielectric capacitor of high integration degree is manufactured by forming a bottom electrode 46 and a top-electrode 48 comprising a homogeneous thin Ru film with 100% step coverage while putting a dielectric 47 therebetween on substrates 44, 45 having a three-dimensional structure with an aspect ratio of 3 or more by a MOCVD process using a cyclopentadienyl complex within a temperature range from 180° C. or higher to 250° C. or lower.

Abstract: A semiconductor device containing a dielectric capacitor having an excellent step coverage for a device structure of high aspect ratio corresponding to high integration degree, as well as a manufacturing method therefor are provided. A dielectric capacitor of high integration degree is manufactured by forming a bottom electrode 46 and a top-electrode 48 comprising a homogeneous thin Ru film with 100% step coverage while putting a dielectric 47 therebetween on substrates 44, 45 having a three-dimensional structure with an aspect ratio of 3 or more by a MOCVD process using a cyclopentadienyl complex within a temperature range from 180° C. or higher to 250° C. or lower.

Abstract: A ferroelectric capacitor of the type having a top electrode, a ferroelectric thin film, and a bottom electrode, is characterized in that said ferroelectric thin film is a perovskite-type oxide containing Pb and said upper and bottom electrodes contain an intermetallic compound composed of Pt and Pb. An electronic device is provided with said ferroelectric capacitor. This construction is designed to solve the following problems. In a non-volatile ferroelectric memory (FeRAM), a degraded layer occurs near the interface between the PZT and the electrode due to hydrogen evolved during processing or due to diffusion of Pb from the PZT into the electrode. A stress due to a difference in lattice constant occurs in the interface between the electrode and the ferroelectric thin film. The degraded layer and the interfacial stress deteriorate the initial polarizing characteristics of the ferroelectric capacitor and also greatly deteriorate the polarizing characteristics after switching cycles.

Abstract: A ferroelectric material readily forms a liquid phase with an alkali metal such as Li, Na, or K (an capacitor of Group Ia) added thereto. The liquid phase reaction takes place at a bottom temperature than the solid-solid reaction. The ferroelectric material crystallizes through the liquid phase reaction. Thus it is possible to crystallize the ferroelectric material without reaction between it and its adjacent electrodes by annealing temperature at 350-500° C. which is bottom than before. Also, a ferroelectric material can be crystallized at a bottom temperature if it is added to Mg or Ca as an alkaline earth capacitor. As in the case of said ferroelectric, a high-dielectric can be crystallized at a bottom temperature (150-450° C.) if it is added to Li, Na, K, Mg, or Ca. The above-mentioned ferroelectric or high-dielectric is formed into a thin film between an top and bottom electrodes so as to produce a ferroelectric capacitor or high-dielectric capacitor.

Abstract: A ferroelectric capacitor of the type having a top electrode, a ferroelectric thin film, and a bottom electrode, is characterized in that said ferroelectric thin film is a perovskite-type oxide containing Pb and said upper and bottom electrodes contain an intermetallic compound composed of Pt and Pb. An electronic device is provided with said ferroelectric capacitor. This construction is designed to solve the following problems. In a non-volatile ferroelectric memory (FeRAM), a degraded layer occurs near the interface between the PZT and the electrode due to hydrogen evolved during processing or due to diffusion of Pb from the PZT into the electrode. A stress due to a difference in lattice constant occurs in the interface between the electrode and the ferroelectric thin film. The degraded layer and the interfacial stress deteriorate the initial polarizing characteristics of the ferroelectric capacitor and also greatly deteriorate the polarizing characteristics after switching cycles.

Abstract: In a semiconductor device and production method thereof, a technique is used to prevent film separation of the bottom electrode occurring during a heat treatment process which is carried out to make the bottom electrode closely packed and in the heat treatment process for producing dielectric crystallization. In the production method, a glue layer including an insulator is formed between SiO2 insulation layer and the inner wall of a concave hole. The SiO2 layer 14 is located on the Si board 11, and Si plug 12 and a barrier layer 13 are formed therein. A glue layer 16 is formed on the inner wall of the hole of the SiO2 insulation layer 15, and a bottom electrode 17 comprising Ru is formed on the barrier layer 13 and glue layer 16. Dielectric film 18 comprising BST and a top electrode 19 comprising Ru are laminated sequentially on the bottom electrode 17, to form a dielectric device with the bottom electrode 17.

Abstract: A power generation gas turbine includes first stage turbine blades made of an alloy whose 10.sup.5 -hour 14-kgf/mm.sup.2 temperature capacity is 920.degree. C. or over, second and subsequent stage turbine blades made of an alloy whose 10.sup.5 -hour 14-kgf/mm.sup.2 temperature capacity is 800.degree. C. or over, first stage turbine nozzles made of an alloy whose 10.sup.5 -hour 6 kgf/mm.sup.2 temperature capacity is 900.degree. C. or over, and second and subsequent stage turbine nozzles made of an alloy whose 10.sup.5 -hour 6-kgf/mm.sup.2 temperature capacity is 800.degree. C. or over.

Abstract: A beam controller for controlling a semiconductor laser provided in an optical recording/playback apparatus includes first and second current sources for driving the semiconductor laser at a low level (play-back mode) and/or at a high level (recording or erasing mode). The first and second current sources are controlled to have stable power automatically by a first and second auto-power circuits, respectively. The first and second auto-power control circuits include a sample-hold circuit which stores an output signal from a low-pass filter. This enables the beam controller to avoid the transition response problems of the low-pass filter. A switching circuit is also included to select either the stored low-pass filter signal on the present low-pass filter signal.

Abstract: A beam controller for controlling a semiconductor laser included in an optical recording-play-back apparatus. The beam controller is comprised of first and second current sources for driving the semiconductor laser at a low level during a play-back mode and at a high level during an erasing mode. The first and second current sources are respectively automatically controlled by a first and second auto-power control circuit to provide stable power outputs.

Abstract: There is disclosed a valve comprising one valve seat ring, of a disc or a body, having a surface composed of a Cr-Mn-Fe system or a Cr-Ni-Fe system Fe-based precipitation hardening type alloy, and another valve seat ring thereof having a surface composed of a Cr-Ni system Ni-based alloy having a hardness Hv of 400 or more.The valves of this invention can have excellent wear resistance, cavitation erosion resistance and galling resistance, and since emitting no cobalt, the valves of this invention are suitable for various plants such as chemical plants, particularly nuclear power plants.

Abstract: In-tube component material for an electronic tube such as a color cathode ray tube, of low thermal expansion coefficient and grain size 2,000-40,000 grains/mm.sup.2, containing Fe as the main constituent and 25-45 wt % Ni, 0.3-10 wt % Cr, and 0-10 wt % Co, and a method of manufacturing it.

Abstract: Color picture tube in which a tube element, e.g., the shadow mask, is constituted by an Fe alloy to which 25-45 wt % of Ni and at least some Cr are added. A Cr rich layer is formed on the tube element surface and black oxide film with a spinel structure containing Cr is formed on the surface of this film.

Abstract: A printing wire comprises a wire main body made of a sintered super hard alloy containing a hard alloy powder, whose major constituent is carbide powder, and a binder phase comprising at least one element selected from the group consisting of nickel and cobalt; and an alloy layer formed on the entire surface of the wire main body, which contains nickel as a major constituent and has nickel phosphide or nickel boride precipitated therein, or an alloy layer which contains cobalt as a major constituent and has cobalt phosphide or cobalt boride precipitated therein.

Abstract: An actuator is arranged such that an operation stroke is obtained by a shape memory element made of a shape memory alloy member for recovering a memorized shape when the shape memory alloy member is heated, and that shape recovery control of the shape memory element is performed by Joule heat generated by a current supplied thereto. The shape memory element of this actuator has a mechanism such as conductive layers made of copper-plated layers covering part of the surface of the shape memory alloy. This mechanism decreases an electrical resistance of at least one portion of the element such that it is smaller than the electrical resistance of any other portion thereof. The conductive layers contribute to the partial shape recovery control of the shape memory element with high precision.