Patents by Inventor Tetsuo Hironaka
Tetsuo Hironaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9214209Abstract: Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections.Type: GrantFiled: November 24, 2014Date of Patent: December 15, 2015Assignee: TAIYO YUDEN CO., LTD.Inventors: Takashi Ishiguro, Masayuki Sato, Tetsuo Hironaka, Masato Inagi
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Publication number: 20150103612Abstract: Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections.Type: ApplicationFiled: November 24, 2014Publication date: April 16, 2015Applicant: TAIYO YUDEN CO., LTD.Inventors: Takashi ISHIGURO, Masayuki SATO, Tetsuo HIRONAKA, Masato INAGI
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Patent number: 8964460Abstract: A semiconductor device of this invention has an array of non-volatile memory cells, may operate immediately after power activation to write data on and read out the data without reading from an external portion. Further, this invention is free from the lithographic process of the phase-change layer on the manufacturing process.Type: GrantFiled: December 5, 2012Date of Patent: February 24, 2015Assignee: Taiyo Yuden Co., Ltd.Inventors: Takashi Ishiguro, Kenichi Shimomai, Kyoko Nakajima, Tetsuo Hironaka, Kazuya Tanigawa
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Patent number: 8952721Abstract: Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections.Type: GrantFiled: June 13, 2011Date of Patent: February 10, 2015Assignee: Taiyo Yuden Co., Ltd.Inventors: Takashi Ishiguro, Masayuki Sato, Tetsuo Hironaka, Hitoshi Shimazaki
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Publication number: 20140071749Abstract: A semiconductor device of this invention has an array of non-volatile memory cells, may operate immediately after power activation to write data on and read out the data without reading from an external portion. Further, this invention is free from the lithographic process of the phase-change layer on the manufacturing process.Type: ApplicationFiled: December 5, 2012Publication date: March 13, 2014Applicant: TAIYO YUDEN CO., LTD.Inventors: Takashi Ishiguro, Kenichi Shimomai, Kyoko Nakajima, Tetsuo Hironaka, Kazuya Tanigawa
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Publication number: 20130100750Abstract: Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections.Type: ApplicationFiled: June 13, 2011Publication date: April 25, 2013Applicant: TAIYO YUDEN CO., LTD.Inventors: Takashi Ishiguro, Masayuki Sato, Tetsuo Hironaka, Masato Inagi, Hitoshi Shimazaki
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Patent number: 8283945Abstract: FPGAs and MPLDs, which are conventional programmable semiconductor devices, have had poor cost performance and did not suitably take long signal lines into account. To solve this, a flip-flop is built into each MLUT block comprised of a plurality of MLUTs, each MLUT comprising a memory and an address-data pair. With respect to the adjacent line between adjacent MLUTs, alternated adjacent line are introduced, while in the case of interconnects between non-adjacent MLUTs, dedicated distant line and, furthermore, a torus interconnect network are provided.Type: GrantFiled: March 24, 2010Date of Patent: October 9, 2012Assignee: Taiyo Yuden Co., Ltd.Inventors: Tetsuo Hironaka, Kazuya Tanigawa, Hiroaki Toguchi, Naoki Hirakawa, Takashi Ishiguro, Masayuki Sato
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Publication number: 20120007635Abstract: FPGAs and MPLDs, which are conventional programmable semiconductor devices, have had poor cost performance and did not suitably take long signal lines into account. To solve this, a flip-flop is built into each MLUT block comprised of a plurality of MLUTs, each MLUT comprising a memory and an address-data pair. With respect to the adjacent line between adjacent MLUTs, alternated adjacent line are introduced, while in the case of interconnects between non-adjacent MLUTs, dedicated distant line and, furthermore, a torus interconnect network are provided.Type: ApplicationFiled: March 24, 2010Publication date: January 12, 2012Applicant: TAIYO YUDEN CO., LTD.Inventors: Tetsuo Hironaka, Kazuya Tanigawa, Hiroaki Toguchi, Naoki Hirakawa, Takashi Ishiguro, Masayuki Sato
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Patent number: 7694077Abstract: A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.Type: GrantFiled: February 20, 2008Date of Patent: April 6, 2010Assignee: Semiconductor Technology Academic Research CenterInventors: Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide, Tai Hirakawa, Koh Johguchi
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Publication number: 20080222360Abstract: A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.Type: ApplicationFiled: February 20, 2008Publication date: September 11, 2008Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTERInventors: Tetsuo Hironaka, Hans Jurgen Mattausch, Tetsushi Koide, Tai Hirakawa, Koh Johguchi
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Patent number: 7360024Abstract: A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.Type: GrantFiled: October 15, 2003Date of Patent: April 15, 2008Assignee: Semiconductor Technology Academic Research CenterInventors: Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide, Tai Hirakawa, Koh Johguchi
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Patent number: 7178008Abstract: A parallel processor has a plurality of operation units that execute operation instructions, and a multi-bank register file in which a plurality of banks each having a plurality of registers are formed. Each of machine instructions, which are input simultaneously, is split into a plurality of nano-instructions each of which includes at least one of an access instruction and operation instruction. The output clock cycles of operation instructions with respect to the operation units are arbitrated. Furthermore, the output clock cycles of access instructions to the multi-bank register file are arbitrated so as to prevent access instructions from contending in an identical bank in the multi-bank register file.Type: GrantFiled: February 18, 2003Date of Patent: February 13, 2007Assignee: Semiconductor Technology Academic Research CenterInventors: Tetsuo Hironaka, Mattausch Hans Juergen, Takeshi Hiramatsu
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Patent number: 7117291Abstract: In a synchronous multi-port bank memory, registers/buffers receive a read/write signal and an address signal from each of external ports, receive and send a data signal to and from each of the external ports, and receive and send a port block signal. An access conflict management circuit receives the address signals from the registers and buffers and generates the port block signal when an access conflict to the bank occurs. A switching network receives the read/write signal and the address signal from the registers/buffers and generates a bank selection signal when no port block signal is received, so as to activate the selected bank. Thus, memory access cycle time is shortened. A synchronous 1-port bank memory is also constructed similarly.Type: GrantFiled: February 27, 2004Date of Patent: October 3, 2006Assignee: Semiconductor Technology Academic Research CenterInventors: Hans Jurgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Hiroshi Uchida, Koh Johguchi, Zhaomin Zhu
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Publication number: 20050125594Abstract: In a synchronous multi-port bank memory, registers/buffers receive a read/write signal and an address signal from each of external ports, receive and send a data signal to and from each of the external ports, and receive and send a port block signal. An access conflict management circuit receives the address signals from the registers and buffers and generates the port block signal when an access conflict to the bank occurs. A switching network receives the read/write signal and the address signal from the registers/buffers and generates a bank selection signal when no port block signal is received, so as to activate the selected bank. Thus, memory access cycle time is shortened. A synchronous 1-port bank memory is also constructed similarly.Type: ApplicationFiled: February 27, 2004Publication date: June 9, 2005Inventors: Hans Mattausch, Tetsushi Koide, Tetsuo Hironaka, Hiroshi Uchida, Koh Johguchi, Zhaomin Zhu
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Publication number: 20040088489Abstract: A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.Type: ApplicationFiled: October 15, 2003Publication date: May 6, 2004Applicant: Semiconductor Technology Academic Research CenterInventors: Tetsuo Hironaka, Hans Jurgen Mattausch, Tetsushi Koide, Tai Hirakawa, Koh Johguchi
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Publication number: 20030200422Abstract: A parallel processor has a plurality of operation units that execute operation instructions, and a multi-bank register file in which a plurality of banks each having a plurality of registers are formed. Each of simultaneously input machine instructions is split into a plurality of nano-instructions each of which includes at least one of an access instruction and operation instruction. The output clock cycles of operation instructions with respect to the operation units are arbitrated. Furthermore, the output clock cycles of access instructions to the multi-bank register file are arbitrated so as to prevent access instructions from contending in an identical bank in the multi-bank register file.Type: ApplicationFiled: February 18, 2003Publication date: October 23, 2003Applicant: Semiconductor Technology Academic Research CenterInventors: Tetsuo Hironaka, Mattausch Hans Juergen, Takeshi Hiramatsu
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Patent number: 4452996Abstract: Di(meth)acrylate esters of the formula: ##STR1## wherein m and n each represents O or an integer of 1 to 3, the average sum of m+n being 1 to 6 and R represents hydrogen or a methyl group, and process for producing the same.The esters are copolymerizable with other unsaturated compounds to form radiation hardenable films with a reduced irritating effect.Type: GrantFiled: January 27, 1983Date of Patent: June 5, 1984Assignee: Nippon Kayaku Kabushiki KaishaInventors: Minoru Yokoshima, Kazuyoshi Nawata, Tetsuo Hironaka, Hideaki Takahashi