Patents by Inventor Tetsuo Izawa
Tetsuo Izawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7005755Abstract: A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.Type: GrantFiled: December 29, 2003Date of Patent: February 28, 2006Assignee: Fujitsu LimitedInventors: Tetsuo Yoshimura, Shinji Kuzuya, Kazuo Sukegawa, Tetsuo Izawa
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Semiconductor device and method for fabricating the same including interconnection of two electrodes
Patent number: 6849511Abstract: A semiconductor device comprises a first transistor 38a having a first gate electrode 22; a second transistor 38b having a second gate electrode 34 which is different from the first gate electrode; an insulation film 28 formed between the first gate electrode and the second gate electrode; and an interconnection electrode 44 buried in a concavity 42 formed in the first gate electrode, the second gate electrode and the insulation film and electrically interconnecting the first gate electrode and the second gate electrode. The interconnection electrode is buried in the concavity formed in the first gate electrode, the second gate electrode and the insulation film, and the interconnection electrodes electrically interconnects the first gate electrode and the second gate electrode, whereby the semiconductor device can have high integration and can be reliable.Type: GrantFiled: April 7, 2004Date of Patent: February 1, 2005Assignee: Fujitsu LimitedInventors: Yasunori Iriyama, Tetsuo Izawa -
Publication number: 20040188726Abstract: A semiconductor device comprises a first transistor 38a having a first gate electrode 22; a second transistor 38b having a second gate electrode 34 which is different from the first gate electrode; an insulation film 28 formed between the first gate electrode and the second gate electrode; and an interconnection electrode 44 buried in a concavity 42 formed in the first gate electrode, the second gate electrode and the insulation film and electrically interconnecting the first gate electrode and the second gate electrode. The interconnection electrode is buried in the concavity formed in the first gate electrode, the second gate electrode and the insulation film, and the interconnection electrodes electrically interconnects the first gate electrode and the second gate electrode, whereby the semiconductor device can have high integration and can be reliable.Type: ApplicationFiled: April 7, 2004Publication date: September 30, 2004Applicant: Fujitsu LimitedInventors: Yasunori Iriyama, Tetsuo Izawa
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Patent number: 6784472Abstract: A semiconductor device comprises a first transistor 38a having a first gate electrode 22; a second transistor 38b having a second gate electrode 34 which is different from the first gate electrode; an insulation film 28 formed between the first gate electrode and the second gate electrode; and an interconnection electrode 44 buried in a concavity 42 formed in the first gate electrode, the second gate electrode and the insulation film and electrically interconnecting the first gate electrode and the second gate electrode. The interconnection electrode is buried in the concavity formed in the first gate electrode, the second gate electrode and the insulation film, and the interconnection electrodes electrically interconnects the first gate electrode and the second gate electrode, whereby the semiconductor device can have high integration and can be reliable.Type: GrantFiled: August 16, 2002Date of Patent: August 31, 2004Assignee: Fujitsu LimitedInventors: Yasunori Iriyama, Tetsuo Izawa
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Publication number: 20040135226Abstract: A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.Type: ApplicationFiled: December 29, 2003Publication date: July 15, 2004Applicant: FUJITSU LIMITEDInventors: Tetsuo Yoshimura, Shinji Kuzuya, Kazuo Sukegawa, Tetsuo Izawa
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Patent number: 6706610Abstract: A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.Type: GrantFiled: August 30, 2002Date of Patent: March 16, 2004Assignee: Fujitsu LimitedInventors: Tetsuo Yoshimura, Shinji Kuzuya, Kazuo Sukegawa, Tetsuo Izawa
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Publication number: 20030008472Abstract: A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.Type: ApplicationFiled: August 30, 2002Publication date: January 9, 2003Applicant: FUJITSU LIMITEDInventors: Tetsuo Yoshimura, Shinji Kuzuya, Kazuo Sukegawa, Tetsuo Izawa
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Publication number: 20030003666Abstract: A semiconductor device comprises a first transistor 38a having a first gate electrode 22; a second transistor 38b having a second gate electrode 34 which is different from the first gate electrode; an insulation film 28 formed between the first gate electrode and the second gate electrode; and an interconnection electrode 44 buried in a concavity 42 formed in the first gate electrode, the second gate electrode and the insulation film and electrically interconnecting the first gate electrode and the second gate electrode. The interconnection electrode is buried in the concavity formed in the first gate electrode, the second gate electrode and the insulation film, and the interconnection electrodes electrically interconnects the first gate electrode and the second gate electrode, whereby the semiconductor device can have high integration and can be reliable.Type: ApplicationFiled: August 16, 2002Publication date: January 2, 2003Applicant: FUJITSU LIMITEDInventors: Yasunori Iriyama, Tetsuo Izawa
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Patent number: 5850096Abstract: A method for fabricating a semiconductor integrated circuit includes the steps of providing a conductor film on a substrate, providing an insulator film on the conductor film to form a layered structure, removing the insulator film selectively from a first part thereof corresponding to a conductor pattern to be formed, while remaining the insulator film on a second part thereof corresponding also to a conductor pattern to be formed, patterning the layered structure to form a conductor pattern defined by side walls, providing a side wall insulation to each of the side walls of the conductor pattern, providing a first local interconnect pattern on the first part of the conductor pattern such that the first local interconnect pattern establishes an electrical connection with the conductor pattern at the first part, and providing a second local interconnect pattern on the second part of the conductor pattern such that the second local interconnect pattern bridges across the conductor pattern at the second part, wType: GrantFiled: February 23, 1995Date of Patent: December 15, 1998Assignee: Fujitsu LimitedInventors: Tetsuo Izawa, Hiroshi Goto, Koichi Hashimoto
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Patent number: 5843841Abstract: A method for fabricating a semiconductor integrated circuit includes the steps of providing a conductor film on a substrate, providing an insulator film on the conductor film to form a layered structure, removing the insulator film selectively from a first part thereof corresponding to a conductor pattern to be formed, while remaining the insulator film on a second part thereof corresponding also to a conductor pattern to be formed, patterning the layered structure to form a conductor pattern defined by side walls, providing a side wall insulation to each of the side walls of the conductor pattern, providing a first local interconnect pattern on the first part of the conductor pattern such that the first local interconnect pattern establishes an electrical connection with the conductor pattern at the first part, and providing a second local interconnect pattern on the second part of the conductor pattern such that the second local interconnect pattern bridges across the conductor pattern at the second part, wType: GrantFiled: June 10, 1996Date of Patent: December 1, 1998Assignee: Fujitsu LimitedInventors: Tetsuo Izawa, Hiroshi Goto, Koichi Hashimoto
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Patent number: 5635426Abstract: On a semiconductor substrate with an exposed silicon region, a metal layer such as Co is deposited and a silicide layer is formed by heat treatment. Thereafter, a metal layer such as Ni and a silicon layer are deposited, and one of them is patterned. The metal layer and silicon layer are heated for silicification to form a local interconnect. A semiconductor device manufacturing method is provided which uses salicide technique and can form a local interconnect of good quality.Type: GrantFiled: September 14, 1995Date of Patent: June 3, 1997Assignee: Fujitsu LimitedInventors: Hiromi Hayashi, Atsuo Fushida, Tetsuo Izawa, Masaki Katsube, Tatsuya Yamazaki
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Patent number: 5296727Abstract: A high speed and highly functional MOSFET having a thin channel formed in a single crystalline layer is controlled by voltages applied to both an upper gate electrode and a buried gate layer that sandwich the channel therebetween.Type: GrantFiled: May 5, 1993Date of Patent: March 22, 1994Assignee: Fujitsu LimitedInventors: Shinichi Kawai, Tetsuo Izawa
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Patent number: 4091545Abstract: For the purpose of utilizing as a sinter raw material a rolling mill sludge with a grease deposit having a high moisture content, which is deposited in a waste water pit of a steel rolling mill, the moisture content of said rolling mill sludge is reduced to from about 1% to 10% by drying said rolling mill sludge at a temperature of from about 120.degree. C to about 200.degree. C, preferably of about 140.degree. C to about 150.degree.Type: GrantFiled: July 8, 1977Date of Patent: May 30, 1978Assignee: Nippon Kokan Kabushiki KaishaInventors: Tetsuo Izawa, Shuji Kajikawa, Koji Satomi, Koichiro Nakano, Shinichi Kurosawa, Keitaro Hirai, Yuichi Tsukada