Patents by Inventor Tetsuo Izawa

Tetsuo Izawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7005755
    Abstract: A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: February 28, 2006
    Assignee: Fujitsu Limited
    Inventors: Tetsuo Yoshimura, Shinji Kuzuya, Kazuo Sukegawa, Tetsuo Izawa
  • Patent number: 6849511
    Abstract: A semiconductor device comprises a first transistor 38a having a first gate electrode 22; a second transistor 38b having a second gate electrode 34 which is different from the first gate electrode; an insulation film 28 formed between the first gate electrode and the second gate electrode; and an interconnection electrode 44 buried in a concavity 42 formed in the first gate electrode, the second gate electrode and the insulation film and electrically interconnecting the first gate electrode and the second gate electrode. The interconnection electrode is buried in the concavity formed in the first gate electrode, the second gate electrode and the insulation film, and the interconnection electrodes electrically interconnects the first gate electrode and the second gate electrode, whereby the semiconductor device can have high integration and can be reliable.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: February 1, 2005
    Assignee: Fujitsu Limited
    Inventors: Yasunori Iriyama, Tetsuo Izawa
  • Publication number: 20040188726
    Abstract: A semiconductor device comprises a first transistor 38a having a first gate electrode 22; a second transistor 38b having a second gate electrode 34 which is different from the first gate electrode; an insulation film 28 formed between the first gate electrode and the second gate electrode; and an interconnection electrode 44 buried in a concavity 42 formed in the first gate electrode, the second gate electrode and the insulation film and electrically interconnecting the first gate electrode and the second gate electrode. The interconnection electrode is buried in the concavity formed in the first gate electrode, the second gate electrode and the insulation film, and the interconnection electrodes electrically interconnects the first gate electrode and the second gate electrode, whereby the semiconductor device can have high integration and can be reliable.
    Type: Application
    Filed: April 7, 2004
    Publication date: September 30, 2004
    Applicant: Fujitsu Limited
    Inventors: Yasunori Iriyama, Tetsuo Izawa
  • Patent number: 6784472
    Abstract: A semiconductor device comprises a first transistor 38a having a first gate electrode 22; a second transistor 38b having a second gate electrode 34 which is different from the first gate electrode; an insulation film 28 formed between the first gate electrode and the second gate electrode; and an interconnection electrode 44 buried in a concavity 42 formed in the first gate electrode, the second gate electrode and the insulation film and electrically interconnecting the first gate electrode and the second gate electrode. The interconnection electrode is buried in the concavity formed in the first gate electrode, the second gate electrode and the insulation film, and the interconnection electrodes electrically interconnects the first gate electrode and the second gate electrode, whereby the semiconductor device can have high integration and can be reliable.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: August 31, 2004
    Assignee: Fujitsu Limited
    Inventors: Yasunori Iriyama, Tetsuo Izawa
  • Publication number: 20040135226
    Abstract: A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.
    Type: Application
    Filed: December 29, 2003
    Publication date: July 15, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuo Yoshimura, Shinji Kuzuya, Kazuo Sukegawa, Tetsuo Izawa
  • Patent number: 6706610
    Abstract: A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: March 16, 2004
    Assignee: Fujitsu Limited
    Inventors: Tetsuo Yoshimura, Shinji Kuzuya, Kazuo Sukegawa, Tetsuo Izawa
  • Publication number: 20030008472
    Abstract: A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.
    Type: Application
    Filed: August 30, 2002
    Publication date: January 9, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuo Yoshimura, Shinji Kuzuya, Kazuo Sukegawa, Tetsuo Izawa
  • Publication number: 20030003666
    Abstract: A semiconductor device comprises a first transistor 38a having a first gate electrode 22; a second transistor 38b having a second gate electrode 34 which is different from the first gate electrode; an insulation film 28 formed between the first gate electrode and the second gate electrode; and an interconnection electrode 44 buried in a concavity 42 formed in the first gate electrode, the second gate electrode and the insulation film and electrically interconnecting the first gate electrode and the second gate electrode. The interconnection electrode is buried in the concavity formed in the first gate electrode, the second gate electrode and the insulation film, and the interconnection electrodes electrically interconnects the first gate electrode and the second gate electrode, whereby the semiconductor device can have high integration and can be reliable.
    Type: Application
    Filed: August 16, 2002
    Publication date: January 2, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Yasunori Iriyama, Tetsuo Izawa
  • Patent number: 5850096
    Abstract: A method for fabricating a semiconductor integrated circuit includes the steps of providing a conductor film on a substrate, providing an insulator film on the conductor film to form a layered structure, removing the insulator film selectively from a first part thereof corresponding to a conductor pattern to be formed, while remaining the insulator film on a second part thereof corresponding also to a conductor pattern to be formed, patterning the layered structure to form a conductor pattern defined by side walls, providing a side wall insulation to each of the side walls of the conductor pattern, providing a first local interconnect pattern on the first part of the conductor pattern such that the first local interconnect pattern establishes an electrical connection with the conductor pattern at the first part, and providing a second local interconnect pattern on the second part of the conductor pattern such that the second local interconnect pattern bridges across the conductor pattern at the second part, w
    Type: Grant
    Filed: February 23, 1995
    Date of Patent: December 15, 1998
    Assignee: Fujitsu Limited
    Inventors: Tetsuo Izawa, Hiroshi Goto, Koichi Hashimoto
  • Patent number: 5843841
    Abstract: A method for fabricating a semiconductor integrated circuit includes the steps of providing a conductor film on a substrate, providing an insulator film on the conductor film to form a layered structure, removing the insulator film selectively from a first part thereof corresponding to a conductor pattern to be formed, while remaining the insulator film on a second part thereof corresponding also to a conductor pattern to be formed, patterning the layered structure to form a conductor pattern defined by side walls, providing a side wall insulation to each of the side walls of the conductor pattern, providing a first local interconnect pattern on the first part of the conductor pattern such that the first local interconnect pattern establishes an electrical connection with the conductor pattern at the first part, and providing a second local interconnect pattern on the second part of the conductor pattern such that the second local interconnect pattern bridges across the conductor pattern at the second part, w
    Type: Grant
    Filed: June 10, 1996
    Date of Patent: December 1, 1998
    Assignee: Fujitsu Limited
    Inventors: Tetsuo Izawa, Hiroshi Goto, Koichi Hashimoto
  • Patent number: 5635426
    Abstract: On a semiconductor substrate with an exposed silicon region, a metal layer such as Co is deposited and a silicide layer is formed by heat treatment. Thereafter, a metal layer such as Ni and a silicon layer are deposited, and one of them is patterned. The metal layer and silicon layer are heated for silicification to form a local interconnect. A semiconductor device manufacturing method is provided which uses salicide technique and can form a local interconnect of good quality.
    Type: Grant
    Filed: September 14, 1995
    Date of Patent: June 3, 1997
    Assignee: Fujitsu Limited
    Inventors: Hiromi Hayashi, Atsuo Fushida, Tetsuo Izawa, Masaki Katsube, Tatsuya Yamazaki
  • Patent number: 5296727
    Abstract: A high speed and highly functional MOSFET having a thin channel formed in a single crystalline layer is controlled by voltages applied to both an upper gate electrode and a buried gate layer that sandwich the channel therebetween.
    Type: Grant
    Filed: May 5, 1993
    Date of Patent: March 22, 1994
    Assignee: Fujitsu Limited
    Inventors: Shinichi Kawai, Tetsuo Izawa
  • Patent number: 4091545
    Abstract: For the purpose of utilizing as a sinter raw material a rolling mill sludge with a grease deposit having a high moisture content, which is deposited in a waste water pit of a steel rolling mill, the moisture content of said rolling mill sludge is reduced to from about 1% to 10% by drying said rolling mill sludge at a temperature of from about 120.degree. C to about 200.degree. C, preferably of about 140.degree. C to about 150.degree.
    Type: Grant
    Filed: July 8, 1977
    Date of Patent: May 30, 1978
    Assignee: Nippon Kokan Kabushiki Kaisha
    Inventors: Tetsuo Izawa, Shuji Kajikawa, Koji Satomi, Koichiro Nakano, Shinichi Kurosawa, Keitaro Hirai, Yuichi Tsukada