Patents by Inventor Tetsuo KAWAKAMI

Tetsuo KAWAKAMI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961204
    Abstract: A novel technique is provided that analyzes the state of life using multivariate data relating to life. A state visualization device includes: a coarse-graining portion configured to perform coarse-graining on values corresponding to a plurality of items included in sample data; a model creation portion configured to obtain, using binarized values, a mathematical model for calculating energies each fitting a frequency of occurrence of a state represented by a combination of values corresponding to the items; a graph creation portion configured to create a graph in which the state is placed in two-dimensional space; and an interpolation processing portion configured to create a landscape image by smoothing and interpolating a discrete graph.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: April 16, 2024
    Assignee: RIKEN
    Inventors: Tetsuo Ishikawa, Eiryo Kawakami
  • Patent number: 11049651
    Abstract: An electronic component includes a first external electrode disposed on a first end surface and a second external electrode disposed on a second end surface. The first external electrode includes a first conductive layer including ceramic particles. The second external electrode includes a second conductive layer including ceramic particles. An end portion of a first internal electrode is located inside the first conductive layer. The electronic component includes little or no cracks and has a low equivalent series resistance (ESR).
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 29, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tomohiro Kageyama, Tetsuo Kawakami, Manabu Sakai, Ryuki Kakuta, Takahiro Hirao, Takashi Ohara
  • Patent number: 10438747
    Abstract: A multilayer electronic component includes first, second, and third ceramic layers, first and second inner electrodes, and a via-electrode. The first, second and third ceramic layers are sequentially stacked on each other. The first inner electrode is sandwiched between the first and second ceramic layers. The second inner electrode is sandwiched between the second and third ceramic layers. The via-electrode electrically connects the first and second inner electrodes. A projection is integrally provided with the via-electrode. The projection projects from the via-electrode towards an outer peripheral direction and is inserted into the second ceramic layer in a layered arrangement.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: October 8, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tetsuo Kawakami, Takahiro Hirao, Tsutomu Tanaka, Tomohiro Kageyama
  • Patent number: 10418180
    Abstract: In an electronic component, a first outer electrode includes a first conductive layer provided on a first end surface. A second outer electrode includes a second conductive layer provided on a second end surface. A first inner electrode passes through the first conductive layer. A second inner electrode passes through the second conductive layer.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: September 17, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tomohiro Kageyama, Tetsuo Kawakami, Manabu Sakai, Takashi Ohara, Takahiro Hirao, Ryuki Kakuta
  • Publication number: 20180277305
    Abstract: A multilayer electronic component includes first, second, and third ceramic layers, first and second inner electrodes, and a via-electrode. The first, second and third ceramic layers are sequentially stacked on each other. The first inner electrode is sandwiched between the first and second ceramic layers. The second inner electrode is sandwiched between the second and third ceramic layers. The via-electrode electrically connects the first and second inner electrodes. A projection is integrally provided with the via-electrode. The projection projects from the via-electrode towards an outer peripheral direction and is inserted into the second ceramic layer in a layered arrangement.
    Type: Application
    Filed: March 5, 2018
    Publication date: September 27, 2018
    Inventors: Tetsuo KAWAKAMI, Takahiro HIRAO, Tsutomu TANAKA, Tomohiro KAGEYAMA
  • Patent number: 10079103
    Abstract: A multilayer electronic component includes outer electrodes each including an outer electrode main body electrically conducted to an internal electrode and entering portions that project from the outer electrode main body as a base end and enter into the electronic component element through an end surface of the electronic component element. The entering portions each include a slope relative to a principal surface in a flat region including a major portion of the internal electrode.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: September 18, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tetsuo Kawakami, Takahiro Hirao, Tsutomu Tanaka, Tomohiro Kageyama
  • Publication number: 20180137976
    Abstract: An electronic component includes a first external electrode disposed on a first end surface and a second external electrode disposed on a second end surface. The first external electrode includes a first conductive layer including ceramic particles. The second external electrode includes a second conductive layer including ceramic particles. An end portion of a first internal electrode is located inside the first conductive layer. The electronic component includes little or no cracks and has a low equivalent series resistance (ESR).
    Type: Application
    Filed: November 13, 2017
    Publication date: May 17, 2018
    Inventors: Tomohiro KAGEYAMA, Tetsuo KAWAKAMI, Manabu SAKAI, Ryuki KAKUTA, Takahiro HIRAO, Takashi OHARA
  • Publication number: 20170263383
    Abstract: In an electronic component, a first outer electrode includes a first conductive layer provided on a first end surface. A second outer electrode includes a second conductive layer provided on a second end surface. A first inner electrode passes through the first conductive layer. A second inner electrode passes through the second conductive layer.
    Type: Application
    Filed: March 7, 2017
    Publication date: September 14, 2017
    Inventors: Tomohiro KAGEYAMA, Tetsuo KAWAKAMI, Manabu SAKAI, Takashi OHARA, Takahiro HIRAO, Ryuki KAKUTA
  • Publication number: 20170125167
    Abstract: A multilayer electronic component includes outer electrodes each including an outer electrode main body electrically conducted to an internal electrode and entering portions that project from the outer electrode main body as a base end and enter into the electronic component element through an end surface of the electronic component element. The entering portions each include a slope relative to a principal surface in a flat region including a major portion of the internal electrode.
    Type: Application
    Filed: October 28, 2016
    Publication date: May 4, 2017
    Inventors: Tetsuo KAWAKAMI, Takahiro HIRAO, Tsutomu TANAKA, Tomohiro KAGEYAMA
  • Publication number: 20150332853
    Abstract: A method for manufacturing a ceramic electronic component by forming a dielectric layer by ejecting a dielectric layer ink having a pigment volume concentration of 60% or more and 95% or less with an ink-jet system, forming a conductor layer by ejecting a metal pigment ink having a pigment volume concentration of 70% or more and 95% or less with the ink-jet system, forming a body having a conductor circuit by combining the formed dielectric layer and the formed conductor layer appropriately, removing organic components of the resulting formed body by degreasing, and sintering the dielectric layer and the conductor layer by firing.
    Type: Application
    Filed: May 6, 2015
    Publication date: November 19, 2015
    Inventors: Tomohiro Kageyama, Tetsuo Kawakami, Tsutomu Tanaka, Kenichi Shimazaki, Takahiro Hirao
  • Patent number: 9157896
    Abstract: An ultrasonic flaw detecting apparatus including: a transducer including a piezoelectric element array for transmitting ultrasonic waves to and receiving echo signals from a test object; an element driving unit for scanning the piezoelectric element array at a predetermined cycle and generating the ultrasonic waves; a synthesizing unit for synthesizing an internal image of the test object based on the echo signals received by the piezoelectric element array; and a signal replacing unit for replacing the received echo signal with an echo signal in which a bottom echo of the test object is removed.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: October 13, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshino Ito, Hirokazu Karasawa, Yoshio Ueda, Tsuyoshi Hieda, Tetsuya Yadoguchi, Tetsuo Kawakami, Kouichi Kokubo, Hideo Isobe, Kazuyuki Haruna, Masamitsu Niki
  • Publication number: 20110232386
    Abstract: According to one embodiment, An ultrasonic flaw detecting apparatus comprising: a transducer in which a piezoelectric element array for transmitting ultrasonic waves to and receiving echo signals from a test object; an element driving unit for scanning the piezoelectric element array at a predetermined cycle and causing the ultrasonic waves; a synthesizing unit for synthesizing an internal image of the test object based on the echo signals received by the piezoelectric element array; and a signal replacing unit for replacing the received echo signal with an echo signal in which a bottom echo of the test object is removed.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 29, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshino ITO, Hirokazu KARASAWA, Yoshio UEDA, Tsuyoshi HIEDA, Tetsuya YADOGUCHI, Tetsuo KAWAKAMI, Kouichi KOKUBO, Hideo ISOBE, Kazuyuki HARUNA, Masamitsu NIKI