Patents by Inventor Tetsuo Kumazawa
Tetsuo Kumazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11965123Abstract: A red phosphor that has optical characteristics and durability under high-temperature and high-humidity environments, and a method for producing the same. The red phosphor includes a Mn-activated complex fluoride represented by the following general formula (1) and bismuth: A2MF6:Mn4+??(1) wherein A represents at least one alkali metal element selected from the group consisting of lithium, sodium, potassium, rubidium and cesium, and M represents at least one tetravalent element selected from the group consisting of silicon, germanium, tin, titanium, zirconium and hafnium.Type: GrantFiled: March 19, 2020Date of Patent: April 23, 2024Assignee: STELLA CHEMIFA CORPORATIONInventors: Hiroaki Takatori, Shinya Kumazawa, Tetsuya Arakawa, Tetsuo Nishida
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Patent number: 7198962Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.Type: GrantFiled: April 11, 2003Date of Patent: April 3, 2007Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
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Publication number: 20030203521Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.Type: ApplicationFiled: April 11, 2003Publication date: October 30, 2003Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
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Patent number: 6566150Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.Type: GrantFiled: June 17, 2002Date of Patent: May 20, 2003Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
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Publication number: 20020182796Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.Type: ApplicationFiled: June 17, 2002Publication date: December 5, 2002Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
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Patent number: 6455335Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.Type: GrantFiled: August 31, 2000Date of Patent: September 24, 2002Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
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Patent number: 6297073Abstract: A semiconductor device, is provided will semiconductor chips having a plurality of electrodes for external connection, elastomer resin portions formed of an elastomer resin, which are bonded to the semiconductor chip excepting at least some of the plurality of electrodes, a tape layer of resin including tape wiring patterns on the surface thereof, a plurality of solder bumps for bonding the printed wiring pattern to the tape wiring patterns, leads for connecting the plurality of electrodes of the semiconductor chips to the tape wiring patterns, and seal resin for covering the leads and the plurality of electrodes which are connected by the leads. The elastomer resin has a modulus of transverse elasticity not less than 50 MPa and not more than 750 MPa.Type: GrantFiled: April 11, 2000Date of Patent: October 2, 2001Assignee: Hitachi, Ltd.Inventors: Makoto Kitano, Ryuji Kohno, Naotaka Tanaka, Akihiro Yaguchi, Tetsuo Kumazawa, Ichiro Anjoh, Hideki Tanaka, Asao Nishimura, Shuji Eguchi, Akira Nagai, Mamoru Mita
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Patent number: 6197603Abstract: Dispersion of a load may be kept within a predetermined allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane against a wafer by applying a pressure load to a plurality of places on a plane of the pressure members on the side opposite the wafer in a probe test step, burn-in test step which represent typical semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit at the same time.Type: GrantFiled: September 18, 1998Date of Patent: March 6, 2001Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
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Patent number: 6130112Abstract: A semiconductor device, is provided will semiconductor chips having a plurality of electrodes for external connection, elastomer resin portions formed of an elastomer resin, which are bonded to the semiconductor chip excepting at least some of the plurality of electrodes, a tape layer of resin including tape wiring patterns on the surface thereof, a plurality of solder bumps for bonding the printed wiring pattern to the tape wiring patterns, leads for connecting the plurality of electrodes of the semiconductor chips to the tape wiring patterns, and seal resin for covering the leads and the plurality of electrodes which are connected by the leads. The elastomer resin has a modulus of transverse elasticity not less than 50 MPa and not more than 750 MPa.Type: GrantFiled: October 6, 1998Date of Patent: October 10, 2000Assignee: Hitachi, Ltd.Inventors: Makoto Kitano, Ryuji Kohno, Naotaka Tanaka, Akihiro Yaguchi, Tetsuo Kumazawa, Ichiro Anjoh, Hideki Tanaka, Asao Nishimura, Shuji Eguchi, Akira Nagai, Mamoru Mita
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Patent number: 6049128Abstract: A semiconductor device, is provided will semiconductor chips having a plurality of electrodes for external connection, elastomer resin portions formed of an elastomer resin, which are bonded to the semiconductor chip excepting at least some of the plurality of electrodes, a tape layer of resin including tape wiring patterns on the surface thereof, a plurality of solder bumps for bonding the printed wiring pattern to the tape wiring patterns, leads for connecting the plurality of electrodes of the semiconductor chips to the tape wiring patterns, and seal resin for covering the leads and the plurality of electrodes which are connected by the leads. The elastomer resin has a modulus of transverse elasticity not less than 50 MPa and not more than 750 MPa.Type: GrantFiled: March 19, 1997Date of Patent: April 11, 2000Assignee: Hitachi, Ltd.Inventors: Makoto Kitano, Ryuji Kohno, Naotaka Tanaka, Akihiro Yaguchi, Tetsuo Kumazawa, Ichiro Anjoh, Hideki Tanaka, Asao Nishimura, Shuji Eguchi, Akira Nagai, Mamoru Mita
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Patent number: 5837567Abstract: A lead frame for use with a plastic encapsulated semiconductor device includes a tab on which the semiconductor chip is mounted, chip pad supporting leads, inner leads to be electrically coupled with the semiconductor chip, outer leads formed in a monoblock structure together with the inner leads, and a frame for supporting the chip pad supporting leads and outer leads. In the lead frame, there is disposed a dam member only between the outer leads. Alternatively, dummy outer leads are formed between the frame and leads adjacent thereto so as to connect the dummy leads to the outer leads by the dam member. The frame is removed after the semiconductor device is assembled.Type: GrantFiled: March 31, 1997Date of Patent: November 17, 1998Assignee: Hitachi, Ltd.Inventors: Naotaka Tanaka, Akihiro Yaguchi, Makoto Kitano, Tatsuya Nagata, Tetsuo Kumazawa, Atsushi Nakamura, Hiromichi Suzuki, Masayoshi Tsugane
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Patent number: 5671316Abstract: A connecting structure of an optical fiber to an optical waveguide includes a circular cylindrical holder having a bore with a circular cross-section communicating one end thereof to the other. The protecting layer removal end of the optical fiber is inserted into the bore. An end plane of the protecting layer removal end and a side plane of the holder are co-planar to be connected to an end surface of an optical waveguide.Type: GrantFiled: February 14, 1996Date of Patent: September 23, 1997Assignee: Hitachi Cable, Ltd.Inventors: Toshiya Yuhara, Hisao Iitsuka, Kazuyuki Fukuda, Makoto Shimaoka, Tetsuo Kumazawa
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Patent number: 5637914Abstract: A lead frame for use with a plastic encapsulated semiconductor device includes a tab on which the semiconductor chip is mounted, chip pad supporting leads, inner leads to be electrically coupled with the semiconductor chip, outer leads formed in a monoblock structure together with the inner leads, and a frame for supporting the chip pad supporting leads and outer leads. In the lead frame, there is disposed a dam member only between the outer leads. Alternatively, dummy outer leads are formed between the frame and leads adjacent thereto so as to connect the dummy leads to the outer leads by the dam member. The frame is removed after the semiconductor device is assembled.Type: GrantFiled: May 10, 1995Date of Patent: June 10, 1997Assignee: Hitachi, Ltd.Inventors: Naotaka Tanaka, Akihiro Yaguchi, Makoto Kitano, Tatsuya Nagata, Tetsuo Kumazawa, Atsushi Nakamura, Hiromichi Suzuki, Masayoshi Tsugane
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Patent number: 5608265Abstract: A semiconductor device, provided in a plastic encapsulated package, having a semiconductor chip, a lead and a member for electrically connecting them together. The semiconductor device has one or more first holes respectively extending from one surface of the package to a first side of the lead which is provided inside of the package, and has one or more second holes formed which are aligned with the first holes, respectively, in a manner such that each second hole is extended from the opposing surface of the package to a corresponding location on a second side of the lead and is aligned with a corresponding, opposing first hole, in the package, extending to the first side of the lead. These holes are provided as a plurality of sets of individual pairs of aligned holes respectively extending inwardly, from opposing surfaces of the package, to opposite sides of the corresponding leads.Type: GrantFiled: March 9, 1994Date of Patent: March 4, 1997Assignee: Hitachi, Ltd.Inventors: Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Nae Yoneda, Ryuji Kohno, Naotaka Tanaka, Tetsuo Kumazawa
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Patent number: 5569960Abstract: An electronic component unit is provided with two electronic components which are disposed in parallel with each other and each of which has an internal electric circuit therein. Electrode pads are provided on the opposed surfaces of the two electronic components and are electrically connected to the internal electric circuits. The pads on one of the electronic components are respectively electrically and mechanically connected to the corresponding pads on the other electronic component by solder bumps. The areas of the pads increase or decrease stepwise in the direction from the central portions toward the outer peripheral edges of the two electronic components, while the volumes of the solder bumps are constant. Alternatively, the volumes of the solder bumps decrease or increase in the direction from the central portions toward the outer peripheral edges of the two electronic components, while the areas of all pads are constant.Type: GrantFiled: May 10, 1995Date of Patent: October 29, 1996Assignee: Hitachi, Ltd.Inventors: Tetsuo Kumazawa, Makoto Kitano, Akihiro Yaguchi, Ryuji Kohno, Naotaka Tanaka, Nae Yoneda, Ichiro Anjoh
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Patent number: 5195155Abstract: An optical coupling apparatus including a light emitting diode, a lens, an optical isolator and an optical fiber disposed on a common optical axis is improved in the optical coupling efficiency. The individual optical elements are roughly adjusted in the respective positions and fixed, and then a precise and fine adjustment is effectuated by plastically deforming a portion of a holder for supporting the lens or the optical isolator and/or by adjusting inclination of the holder. The holder imparted with the fine adjustment capability can be implemented as a lens holder.Type: GrantFiled: May 21, 1990Date of Patent: March 16, 1993Assignee: Hitachi, Ltd.Inventors: Makoto Shimaoka, Tetsuo Kumazawa, Yasutoshi Yagiu, Atsushi Sasayama
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Patent number: 5046798Abstract: A collimated-beam generating device using a semiconductor laser includes a two-lens system in which light converged by a first lens is converted into a collimated beam by a second lens, whereby a distance between the semiconductor laser and the first lens is made large, assembly of the device is made easy, and a collimated beam having a small beam diameter can be produced.Type: GrantFiled: August 1, 1989Date of Patent: September 10, 1991Assignee: Hitachi, Ltd.Inventors: Yasutoshi Yagiu, Tetsuo Kumazawa, Makoto Shimaoka, Kunio Aiki
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Patent number: 4880290Abstract: An optical fiber apparatus having an optical fiber jacket guide for receiving and guiding an optical fiber therethrough to enable proper optical coupling with an optical component of an opto-electronic package device. An optical fiber core extends through the jacket guide and has a coating material coated thereon and extending within at least a part of the jacket guide. At least a part of the coating material within the jacket guide has an irregular peripheral surface and adhesive within the jacket guide bonds at least the coating material and the jacket guide.Type: GrantFiled: September 21, 1987Date of Patent: November 14, 1989Assignee: Hitachi, Ltd.Inventors: Tetsuo Kumazawa, Makoto Shimaoka, Kazuyuki Fukuda, Eiichi Adachi
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Patent number: 4528223Abstract: Composite fibrous products such as composite cloth, composite strings, composite knitted goods, etc., produced by using combination yarns obtained by twisting one or more aromatic polyamide continuous filament yarns and one or more continuous glass yarns have high rigidity and excellent reinforcing effects.Type: GrantFiled: October 26, 1981Date of Patent: July 9, 1985Assignees: Hitachi, Ltd., Hitachi Chemical Co., Ltd., Fuji Fiber Glass Co., Ltd.Inventors: Tetsuo Kumazawa, Hiroaki Doi, Yasuo Miyadera, Atsushi Fujioka, Tadashi Nagai
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Patent number: 4446191Abstract: A laminate produced by molding under heat and pressure a plurality of prepregs obtained by impregnating a resin into a composite fabric, either woven or nonwoven, comprising aromatic polyamide fibers and glass fibers has a low linear expansion coefficient and excellent interlaminar strength.Type: GrantFiled: October 23, 1981Date of Patent: May 1, 1984Assignees: Hitachi Chemical Company, Ltd., Hitachi, Ltd.Inventors: Yasuo Miyadera, Atsushi Fujioka, Tetsuo Kumazawa, Doi Hiroaki