Abstract: According to one embodiment, a camera includes a camera head, an optical unit, a camera control unit (CCU), a camera head-side connector, and a CCU-side connector. The camera head has an imaging element. The CCU has an image processing circuit that processes image information acquired by the imaging element therein. The camera head-side connector is provided to protrude beyond an outer shape of the camera head. The CCU-side connector is opened in an outer wall of the CCU, and the camera head-side connector is inserted into the CCU-side connector.

Abstract: A logical simulation device has a delay value calculations section to calculate delay values of circuit blocks in a semiconductor integrated circuit as a target of logical simulation based on logical circuit information relating to the logical circuit blocks, input test patterns as operational descriptions of used in circuit verification, and delay value calculation information stored in a delay value and timing check value calculation library, and a logical simulation section performs the logical simulation of the semiconductor integrated circuit based on the calculated delay values.

Abstract: An information processing apparatus has a transmission antenna and a reception antenna and performs radio transmission/reception with a radio card via the two antennas, thereby performing predetermined information processing. Each of the transmission antenna and reception antenna is formed of a loop antenna. Both antennas are made to overlap each other by a predetermined length so as to prevent mutual electromagnetic interference and are situated in substantially the same plane. Accordingly, even if the transmission antenna and reception antenna are situated close to each other, a signal radiated from the transmission antenna is prevented from interfering with the reception antenna. Thus, the reception antenna can surely receive only a signal radiated from the radio card or an object of communication.

Abstract: A first full-wave rectifier circuit generates a power supply voltage from a received modulated radio wave signal and a second full-wave rectifier circuit binarizes the voltage to obtain a binary signal. A continuous clock signal is generated from the binary signal. The modulated radio wave signal is also binarized and demodulated using the continuous clock signal. This demodulation is performed simultaneously with the generation of the power supply voltage. A command can be received continuously and data can be read or written continuously. Therefore, the reception of power or the reception/transmission of data need not be performed intermittently, but rather a large amount of data can be received or transmitted continuously at high speed.

Abstract: A read request signal containing a command, an address, etc. is subjected to two-phase modulation with the first carrier of a first frequency and the resultant signal is then transmitted to a radio card. After the transmission of the read request signal, the first carrier is kept transmitted to the radio card. Upon reception of the read request signal, the radio card generates a power supply voltage and an operation clock and sends response data to the read request signal to a radio card reader/writer. Unlike in the prior art, therefore, the reception of power or the reception/transmission of data need not be performed intermittently so that a large amount of data can be received or transmitted continuously at a high speed.

Abstract: In a digital phase locked loop, a coarse stepsize variable delay line and a fine stepsize variable delay line are connected in series for receiving a reference clock pulse and imparting thereto variable delays in accordance with higher significant bits and lower significant bits. The delayed clock pulse is delivered to the input of a clock tree through which the clock pulse propagates and are supplied to various parts of an integrated circuit chip. A phase detector provides a phase comparison between the reference clock pulse and a delayed clock pulse appearing at one of the outputs of the clock tree. A delay controller counts the reference clock pulse to produce a count value, and increments or decrements the count value in accordance with the output of the phase detector.