Patents by Inventor Tetsuo Shimura

Tetsuo Shimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230352245
    Abstract: A multilayer ceramic electronic device includes a multilayer chip having a plurality of dielectric layers and a plurality of internal electrode layers, one end of each of the plurality of internal electrode layers being exposed from the multilayer chip, an external electrode that is provided on an end face of the multilayer chip and is electrically connected to the one end of at least some of the plurality of internal electrode layers and includes a glass component, the end face being an end of the multilayer chip in a direction in which the plurality of internal electrode layers extend. The external electrode includes a crystal contacting or extending into the glass component at an interface between the external electrode and the end face of the multilayer chip. The crystal includes an element that is the same as at least one of elements included in the plurality of dielectric layers.
    Type: Application
    Filed: April 12, 2023
    Publication date: November 2, 2023
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Yasuyuki INOMATA, Tetsuo SHIMURA, Masaki MOCHIGI
  • Patent number: 11488783
    Abstract: A multilayer ceramic capacitor includes a laminated body in which dielectric layers and internal electrodes are laminated alternately. The dielectric layer includes a first phase that contains calcium strontium zirconate titanate as a main component thereof and a second phase that contains barium zirconate as a main component thereof. At a cross section of the dielectric layer, a line parallel to the direction in which the dielectric layers and the internal electrodes are laminated contacts the boundaries between the first phase and the second phase once or more on average, thereby the statistically averaged contact number N of such a line with the boundaries determined by a prescribed procedure being 1.0 or greater.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: November 1, 2022
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Tetsuo Shimura, Yasuyuki Inomata
  • Patent number: 11282641
    Abstract: A ceramic electronic device includes a multilayer structure in which each of dielectric layers and each of internal electrode layers are alternately stacked, wherein a main component of the dielectric layers is (Ba, Sr, Ca)(Zr, Ti)O3, wherein a Ba concentration and a Ca concentration have variation in at least one of crystal grains in the dielectric layers.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: March 22, 2022
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Tetsuo Shimura, Tomoya Hagiwara, Yasuyuki Inomata
  • Publication number: 20210118615
    Abstract: A ceramic electronic device includes a multilayer structure in which each of dielectric layers and each of internal electrode layers are alternately stacked, wherein a main component of the dielectric layers is (Ba, Sr, Ca)(Zr, Ti)O3, wherein a Ba concentration and a Ca concentration have variation in at least one of crystal grains in the dielectric layers.
    Type: Application
    Filed: September 29, 2020
    Publication date: April 22, 2021
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Tetsuo SHIMURA, Tomoya HAGIWARA, Yasuyuki INOMATA
  • Patent number: 10903012
    Abstract: A ceramic capacitor includes a multilayer structure, wherein a main component of dielectric layers is ceramic expressed by a general formula AmBO3 (0.995?m?1.010), wherein the dielectric layers include a rare earth element Re as a first sub-component by 2.0 mol to 5.0 mol when converted into Re2O3/2, include Mg as a second sub-component by 1.0 mol to 3.0 mol when converted into MgO, include V as a third sub-component by 0.05 mol to 0.25 mol when converted into V2O5/2, include Si as a fourth sub-component by 0.5 mol to 5.0 mol when converted into SiO2, include an alkali earth metal element M as a fifth sub-component by 0.1 mol to 5.0 mol when converted into MCO3, on a presumption that an amount of the ceramic is 100 mol, wherein a ratio Si/V is 30 or less.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: January 26, 2021
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Yasuyuki Inomata, Yousuke Nakada, Tetsuo Shimura
  • Publication number: 20200411249
    Abstract: A multilayer ceramic capacitor includes a laminated body in which dielectric layers and internal electrodes are laminated alternately. The dielectric layer includes a first phase that contains calcium strontium zirconate titanate as a main component thereof and a second phase that contains barium zirconate as a main component thereof. At a cross section of the dielectric layer, a line parallel to the direction in which the dielectric layers and the internal electrodes are laminated contacts the boundaries between the first phase and the second phase once or more on average, thereby the statistically averaged contact number N of such a line with the boundaries determined by a prescribed procedure being 1.0 or greater.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 31, 2020
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Tetsuo Shimura, Yasuyuki Inomata
  • Patent number: 10854390
    Abstract: The present technology provides an electronic component with an interposer, including an electronic component and an interposer. An adhesive section is disposed in an opposing space between a main body of the electronic component and a substrate. When a direction in which first and second external electrodes of the electronic component face each other is a first direction, a direction orthogonal to the first direction is a second direction, and a direction in which the electronic component and the interposer face each other is a third direction, the adhesive section includes a plurality of unitary adhesive sections separated from each other, and the unitary adhesive sections are disposed in a two-dimensional array such that the number of unitary adhesive sections arrayed along the second direction is smaller on opposing sides in the first direction than at a center.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Tetsuo Shimura, Yosuke Nakada, Yasuyuki Inomata
  • Patent number: 10460874
    Abstract: In an embodiment, an electronic component with metal terminals includes: an electronic component 10 having a component body 11 of roughly rectangular solid shape, as well as external electrodes 12 provided on the ends thereof in the first direction d1, respectively; and metal terminals 20 provided in sets of two on each external electrode 12. Each metal terminal 20 has a first planar part 21 and a second planar part 23 oriented differently from the first planar part 21; the first planar part 21 is connected to each external electrode 12 in a manner facing one face of the component body 11; and the second planar part 23 is positioned in a manner facing at least partially, across a clearance 24, another face adjoining the one face of the component body 11, while being fixed to the component body 11 by an adhesive 40 provided in the clearance 24.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: October 29, 2019
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Tetsuo Shimura, Yosuke Nakada
  • Publication number: 20190287723
    Abstract: The present technology provides an electronic component with an interposer, including an electronic component and an interposer. An adhesive section is disposed in an opposing space between a main body of the electronic component and a substrate. When a direction in which first and second external electrodes of the electronic component face each other is a first direction, a direction orthogonal to the first direction is a second direction, and a direction in which the electronic component and the interposer face each other is a third direction, the adhesive section includes a plurality of unitary adhesive sections separated from each other, and the unitary adhesive sections are disposed in a two-dimensional array such that the number of unitary adhesive sections arrayed along the second direction is smaller on opposing sides in the first direction than at a center.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 19, 2019
    Inventors: TETSUO SHIMURA, YOSUKE NAKADA, YASUYUKI INOMATA
  • Publication number: 20190228911
    Abstract: A ceramic capacitor includes a multilayer structure, wherein a main component of dielectric layers is ceramic expressed by a general formula AmBO3 (0.995?m?1.010), wherein the dielectric layers include a rare earth element Re as a first sub-component by 2.0 mol to 5.0 mol when converted into Re2O3/2, include Mg as a second sub-component by 1.0 mol to 3.0 mol when converted into MgO, include V as a third sub-component by 0.05 mol to 0.25 mol when converted into V2O5/2, include Si as a fourth sub-component by 0.5 mol to 5.0 mol when converted into SiO2, include an alkali earth metal element M as a fifth sub-component by 0.1 mol to 5.0 mol when converted into MCO3, on a presumption that an amount of the ceramic is 100 mol, wherein a ratio Si/V is 30 or less.
    Type: Application
    Filed: January 17, 2019
    Publication date: July 25, 2019
    Inventors: Yasuyuki INOMATA, Yousuke NAKADA, Tetsuo SHIMURA
  • Patent number: 10224707
    Abstract: In an embodiment, an electronic component fuse 10 includes: (1) an insulator sleeve 11 having a hollow part 11a that opens to the exterior at both ends; (2) a conductor element 12 having a fusible part 12a whose cross-section is smaller than the cross-section of the hollow part 11a, a first engagement part 12b provided at one end of the fusible part 12a, and a second engagement part 12c provided at the other end of the fusible part 12a, where the fusible part 12a is positioned in the hollow part 11a, the first engagement part 12b and the second engagement part 12c are disposed on the respective ends of the insulator sleeve 11; (3) a first terminal 13 having a first connection part 13a connected to the first engagement part 12b; and (4) a second terminal 14 having a second connection part 14a connected to the second engagement part 12c.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: March 5, 2019
    Assignee: TAIYO YUDEN CO., LTD
    Inventors: Yousuke Nakada, Kenji Matsumoto, Tetsuo Shimura, Kazuya Sato
  • Patent number: 10096425
    Abstract: A multilayer ceramic capacitor includes a laminate constituted by internal electrode layers of different polarities alternately layered via dielectric layers, wherein the multilayer ceramic capacitor is such that the dielectric layers contain ceramic grains whose primary component is BaTiO3, the ceramic grains contain Mo, Mn, rare earth R, and at least one of V and W, and the average valence number of Mo in the ceramic grains is 4.50 to 5.50. The multilayer ceramic capacitor can offer excellent service life characteristics and sufficiently suppress leak current even when the thickness of the dielectric layer is 0.8 ?m or less.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: October 9, 2018
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Chie Kawamura, Yoichiro Ogata, Tetsuo Shimura, Minoru Ryu, Yoshiki Iwazaki
  • Publication number: 20180240595
    Abstract: In an embodiment, an electronic component with metal terminals includes: an electronic component 10 having a component body 11 of roughly rectangular solid shape, as well as external electrodes 12 provided on the ends thereof in the first direction d1, respectively; and metal terminals 20 provided in sets of two on each external electrode 12. Each metal terminal 20 has a first planar part 21 and a second planar part 23 oriented differently from the first planar part 21; the first planar part 21 is connected to each external electrode 12 in a manner facing one face of the component body 11; and the second planar part 23 is positioned in a manner facing at least partially, across a clearance 24, another face adjoining the one face of the component body 11, while being fixed to the component body 11 by an adhesive 40 provided in the clearance 24.
    Type: Application
    Filed: February 20, 2018
    Publication date: August 23, 2018
    Inventors: Tetsuo SHIMURA, Yosuke NAKADA
  • Patent number: 9966193
    Abstract: An electric circuit device connecting first and second external elements, the electric circuit device including: a first electronic component; a first bus bar electrically connected to the first electronic component; a second bus bar electrically connected to the electronic component and overlapped with the first bus bar in a direction perpendicular to main surfaces of the first and second bus bars; a first external terminal electrically connecting the first bus bar to the first external element; a second external terminal electrically connecting the second bus bar to the second external element; a first region in the first external terminal electrically coupled to the first external element; and a second region in the second external terminal electrically coupled to the second external element, and at least partially overlapped with the first region in the direction.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: May 8, 2018
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Kenji Matsumoto, Yousuke Nakada, Tetsuo Shimura, Kazuya Sato
  • Publication number: 20170317484
    Abstract: In an embodiment, an electronic component fuse 10 includes: (1) an insulator sleeve 11 having a hollow part 11a that opens to the exterior at both ends; (2) a conductor element 12 having a fusible part 12a whose cross-section is smaller than the cross-section of the hollow part 11a, a first engagement part 12b provided at one end of the fusible part 12a, and a second engagement part 12c provided at the other end of the fusible part 12a, where the fusible part 12a is positioned in the hollow part 11a, the first engagement part 12b and the second engagement part 12c are disposed on the respective ends of the insulator sleeve 11; (3) a first terminal 13 having a first connection part 13a connected to the first engagement part 12b; and (4) a second terminal 14 having a second connection part 14a connected to the second engagement part 12c.
    Type: Application
    Filed: April 25, 2017
    Publication date: November 2, 2017
    Inventors: Yousuke NAKADA, Kenji MATSUMOTO, Tetsuo SHIMURA, Kazuya SATO
  • Publication number: 20170290161
    Abstract: In an embodiment, a multilayer ceramic capacitor with interposer CWI1 has adhesive material parts 40 provided between the multilayer ceramic capacitor 10 and interposer 20, and the adhesive material parts 40 include space-setting members 41 for setting the spacing between the multilayer ceramic capacitor 10 and interposer 20. The electronic component with interposer can offer an improvement to the issue of its height dimension varying excessively.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 5, 2017
    Inventors: Tetsuo SHIMURA, Yousuke NAKADA
  • Patent number: 9721727
    Abstract: A multilayer ceramic capacitor has a laminate including dielectric layers laminated alternately with internal electrode layers of different polarities, wherein the dielectric layer contains ceramic grains having Ba, Ti, and X (wherein X represents at least one type of element selected from the group consisting of Mo, Ta, Nb, and W) and a variation in the concentration distribution of X above in the ceramic grain is within ±5%. The multilayer ceramic capacitor can offer excellent service life characteristics even when the thickness of the dielectric layer is 0.8 ?m or less, as well as excellent bias characteristics.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: August 1, 2017
    Assignee: TAIYO YUDEN CO., LTD
    Inventors: Chie Kawamura, Tetsuo Shimura, Minoru Ryu, Koichiro Morita, Yukihiro Konishi, Yoshiki Iwazaki
  • Publication number: 20170186551
    Abstract: An electric circuit device connecting first and second external elements, the electric circuit device including: a first electronic component; a first bus bar electrically connected to the first electronic component; a second bus bar electrically connected to the electronic component and overlapped with the first bus bar in a direction perpendicular to main surfaces of the first and second bus bars; a first external terminal electrically connecting the first bus bar to the first external element; a second external terminal electrically connecting the second bus bar to the second external element; a first region in the first external terminal electrically coupled to the first external element; and a second region in the second external terminal electrically coupled to the second external element, and at least partially overlapped with the first region in the direction.
    Type: Application
    Filed: September 20, 2016
    Publication date: June 29, 2017
    Applicant: TAIYO YUDEN CO. LTD.
    Inventors: Kenji MATSUMOTO, Yousuke NAKADA, Tetsuo SHIMURA, Kazuya SATO
  • Patent number: 9679698
    Abstract: A multi-layer ceramic capacitor has a structure where the dispersion, nd, of average grain size of the dielectric grains constituting the dielectric layer (a value (D90/D10) obtained by dividing D90 which is a grain size including 90% cumulative abundance of grains by D10 which is a grain size including 10% cumulative abundance of grains) is smaller than 4.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: June 13, 2017
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Koichiro Morita, Tetsuo Shimura
  • Patent number: RE48877
    Abstract: A multi-layer ceramic capacitor has a structure where the dispersion, nd, of average grain size of the dielectric grains constituting the dielectric layer (a value (D90/D10) obtained by dividing D90 which is a grain size including 90% cumulative abundance of grains by D10 which is a grain size including 10% cumulative abundance of grains) is smaller than 4.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: January 4, 2022
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Koichiro Morita, Tetsuo Shimura