Abstract: An optical and electronic integrated switch includes a network processor that controls the functions of the packet switch, a plurality of optical transceivers having photoelectric conversion functions, and a plurality of optical switches. The optical switches include different types of optical core switch and a plurality of optical-path selection switches. The optical transceivers provided near the processor have a regenerative relay function that regenerates optical signals and turns back the optical signals, and perform optical communication with a communication counterpart via the optical switches. In the optical communication, optical switches of the different types can cooperate to set paths for optical cut-through in which path selection is performed such that inputted optical signals are outputted without the intervention of the processor. This optical cut-through can be effectively performed without imposing a signal processing burden that consumes electric power on the processor.

Abstract: An optical transmission system including an optical transmission device and an optical reception device that receives, via an optical transmission line, a signal transmitted from the optical transmission device, the optical transmission system including a transmission-mode selection unit that selects transmission mode information in descending order of priority out of transmission mode information, which is combinations of a plurality of parameters concerning transmission performance, the transmission mode information being a plurality of kinds of the transmission mode information common to the transmission performance of the optical transmission device and the optical reception device, a signal transmission unit that transmits, to the optical reception device, a signal modulated based on the selected transmission mode information, and a signal reception unit that receives the signal and modulates the received signal based on the transmission mode information selected by the transmission-mode selection unit.

Abstract: An acquisition unit acquires pieces of information including information related to a vehicle, information related to the environment inside and outside the vehicle, and information related to a driver on board the vehicle. A determination unit determines priorities of the pieces of information acquired by the acquisition unit on the basis of a service or the like used by the driver among services or the likes provided using information accumulated in a server device. A selection unit selects a piece of information to be transmitted to the server device from among the pieces of information acquired by the acquisition unit on the basis of the priorities determined by the determination unit. A communication unit transmits the piece of information selected by the selection unit to the server device.

Abstract: A photonics-electronics convergence switch with which, even if an optical network system is built by combining a plurality of packet switches, the amount of processing in the packet switches does not increase, the optical network system operates with low electric power consumption, and this enables wide-range optical communication between the nodes of a communication origin and of a communication partner, includes a network processor that is an electronic circuit configured to control the functions of the packet switch, a plurality of optical transmitter-receivers having photoelectric conversion functions, and a plurality of optical switches.

Abstract: An information processing system including an arithmetic unit in which one unit of data is processed according to a corresponding one instruction, and another arithmetic unit in which a great amount of data are processed according to a corresponding instruction. Also included is an instruction controller which distributes instructions selectively to respective arithmetic units (12) and a main storage (12) which achieves two-way data communication with the arithmetic units. In the system synchronization is performed with respect to instructions, among the aforesaid instructions, which, above all, must be executed in respective fixed execution sequences, by utilizing a newly employed synchronization instruction.

Abstract: The present invention is a data processing system which has plural operation units which can execute plural instructions in parallel. The system also has plural instruction control units each of which comprises at least two stages, one for reading source operands from a local storage, and another for writing a resultant operand into the local storage. Each instruction control unit is provided with specific bank timing signals for accessing the local storage.

Abstract: The present invention discloses a data processing system where a plurality of vector registers consisting of plurality of elements are provided between a main memory unit and an operational processing unit, the desired data is transferred to the vector registers from the main memory unit and is held therein, and various processings such as a logical operation are carried out by sequentially accessing the elements within said vector registers. The present invention also includes a plurality of memory banks which can be independently accessed and are provided for the vector registers. A series of elements of each vector register are interleaved in the plurality of memory banks and the elements having the same numbering in each vector register are arranged in the same memory bank. Timing necessary for starting access to a series of elements of said vector registers are specified for each class of processing, so that the vector operation processings can be done very effectively and without operand collision.

Abstract: A division processing system performs 2N-bit precision division processing by effectively using division processing circuitry with N-bit precision. The system performs the division with 2N-bit precision as follows: ##EQU1## (n=N: the number of digit positions in selected binary numbers A, B, C and D). The above expression is approximated to the form of Q.sub.1 +Q.sub.2 .times.2-n (Q.sub.1, Q.sub.2 : binary numbers). The binary numbers Q.sub.1 and Q.sub.2 are respectively operated on by the division processing circuitry with N-bit precision. By effective control, the error caused during the division processing of Q.sub.1 is used as a part of the data for performing the division processing of Q.sub.2, thus effectively transferring any error evolving during the processing of Q.sub.1 to Q.sub.2.