Abstract: A program-play apparatus in a program-length adjustment system is at least provided with a data separation section for separating video data DPV, a CC-data separation section for separating CC data DPCC, a video memory for temporarily storing the video data DPV, a CC-data memory for temporarily storing the CC data DPCC, and a central processing unit (CPU) for controlling each section. The CPU reads the CC data DPCC stored in the CC-data memory, inserts or deletes meaningless data into or from the CC data DPCC in response to the insertion or deletion of an image constituting the video data stored in the video memory, and outputs as new CC data DRCC.

Abstract: Digital video data recorded in D-1 format, wherein the video data is recorded in successive block units with each block unit being comprised of several segments recorded in plural tracks and with each segment including unit identifying data, is recovered by scanning the tracks with plural sets of reproducing heads to reproduce plural segments concurrently from plural tracks. The unit identifying data in the segments reproduced by all of the reproducing heads in the plural sets are sensed to detect when the unit identifying data in those segments includes common unit identification, thus determining that all of the segments of a preceding block unit have been reproduced from the record medium. That preceding block unit then can be supplied in its entirety to processing or display devices, such as a television monitor.

Abstract: Apparatus for decoding an error detecting or correcting code constructed from digital information data and redundant data for detecting or correcting errors in the digital information data, the digital information data and redundant data being reproduced from a record medium by a playback apparatus that operates in a normal speed mode and fast and slow speed modes, includes a first decoder for decoding the error detecting or correcting code and for generating flag data indicating error conditions of the digital information data, a first memory for storing the digital information data subjected to the decoding in the first decoder, and a second memory for storing flag data.

Abstract: The present invention relates to an error concealing system for digital data in which a reproduced data signal is supplied to error-concealing circuits (34) and (43) and an erroneous data in the reproduced data signal is concealed by the interpolation or substitution using a data near the erroneous data, wherein when the nearby data is erroneous, the nearby data is error-concealed and then fed back to the concealing circuits (34) and (43) to thereby carry out the error concealment so that the erroneous data can sequentially be concealed by using a correct data of small scale.

Abstract: A digital data recording and reproducing device has an operation of error detection performed with respect to data with a code word length of M bits for m.sub.1 most significant bits and for m.sub.2 least significant bits. Error concealment is done for each of these error detections. When reproducing data at a different tape speed from that at the time of recording an operation of detecting an error in the less significant m.sub.2 bits is inhibited, and the reference of judgement of an error in the data is altered.